Abstract: A system comprises pipeline registers and an integrated circuit comprising a memory array. The integrated circuit is coupled to the pipeline registers, and a data path incorporating the memory array is used to test the integrated circuit.

Abstract: A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.

Abstract: A system comprises storage that includes first and second data. The system also comprises circuit logic coupled to the storage. The circuit logic receives a plurality of clock signals. As a result of receiving a signal, the circuit logic uses the plurality of clock signals to obtain the first and second data and to provide the first and second data to target logic coupled to the circuit logic. The system resets the circuit logic between providing the first data and providing the second data.

Abstract: In at least some embodiments, a computing system includes a processor and a debug module coupled to the processor. The debug module controls an emulation environment for debugging code, the emulation environment having a first mode that enables time-critical code to execute while non-time-critical code is halted and a second mode that halts execution of both time-critical code and non-time-critical code. The computing system also includes switch logic in communication with the processor and the debug module, wherein the switch logic enables dynamic switching between the first and second modes.