Abstract: A circuit which increases the speed margin and reduces the circuit size of a programmable RAS/CAS generation circuit. At the beginning of the third cycle {3} in execution cycle (EX), reset signal (reset) is provided to 2-bit counter 52 along with count enable signal (cntenable) and CAS start signal (casstart). In the case of the 0 wait mode, 2-bit counter 52 is operated with count loop (0) and continues to output count value (0). Control signal generating circuit 54 makes CAS.sub.-- active initially midway through the cycle (third cycle {3} during which the count output from 2-bit counter 52 has started and decodes (monitors) the count output (decode0,1,2) from 2-bit counter 52 thereafter with wait count set data (0wait-3wait) as a parameter. In this case, the value of count output (decode0,1,2) is as is at (0), so control signal generating circuit 54 generates CAS.sub.