Abstract: A method for verifying a match between layout patterns of elements provided in a semiconductor integrated circuit, includes a verification condition setting step of setting a verification condition including information about paired elements whose layout patterns should match each other, a layout data input step of inputting layout data including pattern information and arrangement information of the paired elements, and a mismatched pattern parameter calculation layout verifying step of comparing the layout patterns of the paired elements based on the verification condition and the layout data to calculate a distance between the paired elements and at least one mismatched pattern.

Abstract: In a semiconductor integrated circuit mask layout verification method, a layout pattern division condition 108, according to which a plurality of specific layout patterns that need to have identical circuit characteristics are included, is input in a condition input step 109. In a data division step 103, input mask layout design data is divided into a plurality of layout pattern groups according to the layout pattern division condition. In a standard pattern selection step 105, a standard pattern serving as a standard in pattern matching is selected for each of the divided layout pattern groups. In a pattern matching step 106, for each of the layout pattern groups, layout patterns included in that layout pattern group are compared with the standard pattern.

Abstract: An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Abstract: An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Abstract: Based on design data of a semiconductor integrated circuit, an impedance related to a power supply wire is calculated, and based on the calculated impedance, a frequency characteristic of power supply noise is analyzed. In calculation of an impedance, an impedance between power supplies which are different in potential, e.g., a main power supply and a ground, may be calculated. Alternatively, an impedance between power supplies which are substantially the same in potential, e.g., a main power supply and an N-well power supply, may be calculated. The calculated impedance includes a wire capacitance between power supply wires, a substrate resistance, an impedance of a package connected to the power supply wires, and so on. Thus, it is possible to provide a method for analyzing power supply noise of a semiconductor integrated circuit, which can be executed at an early stage of a design process with a small amount of calculation.

Abstract: After a layout for a semiconductor device including power and ground lines has been defined, patterns for bypass capacitors, which will be located under the power lines, are created. In this case, a pattern for a semiconductor device, where a bypass capacitor array is inlaid and substrate contacts are located under ground lines, is defined based on design rules input. Next, power lines are extracted and resized. Thereafter, logical operations are performed to place the bypass capacitors and the bypass capacitors are resized. Subsequently, logical operations are performed to define interconnecting diffused layers and the diffused layers are resized. Since the patterns for the power lines have already been defined before the patterns for the bypass capacitors are created, the patterns for the bypass capacitors to be placed under the power lines can be defined automatically. Thus, a pattern for a miniaturized semiconductor device with reduced power supply noise can be created automatically.