Abstract: A digital multi-level multi-phase modulation system utilizes quaternary differential encoding and decoding of only the first two of N digital signal trains. A decision circuit is used to examine the frame pulses in one of the first two signal trains and in at least one of the remaining signal trains and generates output signals which can be used in a gate circuit to resolve the phase-lock ambiguity of the recovered carrier and thereby reproduce the original N signal trains.

Abstract: A synchronizing circuit for reproducing a synchronizing carrier wave from a received N-phase (N=2.sup.n, n being a positive real integer where n .gtoreq.1) PSK modulated carrier wave and employing a code converter circuit for adjusting the phase states of the received modulated carrier after demodulation thereof in order to enable the modulator to generate signals of the proper phase relation relative to an output carrier wave of a voltage controlled oscillator, which phase relationship is detected by a phase detector.The code converter may be a logic gating circuit having control inputs for changing the output levels or a plurality of branching circuit pairs for each input each pair having a true and complement branch, and switch means for selectively coupling one of the branches to an output associated with each pair of branch circuits.

Abstract: A code error detection system in a digital phase modulation communication system comprises on the transmitter side a first code train generator for generating a pseudo-random code train and a second code train generator for generating codes which are complementary to each other at n-bit intervals. A 4-phase phase modulator is driven by another code representative of the exclusive OR function of the pseudo-random and complementary codes.