Patents by Inventor Seiki Igarashi

Seiki Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240038750
    Abstract: A semiconductor module includes: first and second switching devices coupled in series; a casing housing the first and second switching devices, and having first to fourth edges respectively on first to forth edge sides thereof; positive and negative terminals provided on the first edge side of the casing; an output terminal provided on the second edge side of the casing; a first control terminal and a first sense terminal for the first switching device, and a second control terminal and a second sense terminal for the second switching device, all provided on the third edge side of the casing; first and second conductive patterns respectively coupled to the positive terminal and the output terminal, and on which the first and second switching device are respectively arranged; and a third conductive pattern coupled to the negative terminal and the second switching device, on a side corresponding to the fourth edge side.
    Type: Application
    Filed: June 28, 2023
    Publication date: February 1, 2024
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takuma SAKAI, Seiki IGARASHI
  • Publication number: 20230343756
    Abstract: A laminated wiring has a first conductor which connects first terminals of one or more capacitors and each positive terminal of a plurality of semiconductor modules, a second conductor which connects second terminals of the one or more capacitors and each negative terminal of the plurality of semiconductor modules, and an insulator. Slits are cut in at least one of the first conductor and the second conductor (in both of them in the example of FIG. 1). By doing so, among the plurality of semiconductor modules, a variation in the total of respective inductance values between respective first terminals and one positive terminal closest to the respective first terminals and respective inductance values between respective negative terminals to one second terminal closest to the respective negative terminals becomes smaller than or equal to 10 nH.
    Type: Application
    Filed: March 24, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Seiki IGARASHI
  • Publication number: 20230344361
    Abstract: A semiconductor device includes a first semiconductor module and a second semiconductor module that are connected in parallel between the positive terminal and the negative terminal of a direct-current power source. The first semiconductor module includes a first input terminal electrically connected to the positive terminal, a second input terminal electrically connected to the negative terminal, a first housing, and a first wiring bar that is provided in the first housing and is electrically connected to the first input terminal. The second semiconductor module includes a third input terminal electrically connected to the positive terminal, a fourth input terminal electrically connected to the negative terminal, a second housing, and a second wiring bar that is provided in the second housing, is electrically connected to the fourth input terminal, and is magnetically coupled to the first wiring bar.
    Type: Application
    Filed: February 22, 2023
    Publication date: October 26, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Seiki IGARASHI
  • Patent number: 11621626
    Abstract: A driving apparatus includes: a driving section configured to drive a control terminal of a semiconductor device according to a control signal input from an outside, the semiconductor device including a first main terminal, a second main terminal, and the control terminal that is configured to control a connection state between the first main terminal and the second main terminal that are connected in parallel with a snubber; and a drive control section configured to lower a drive capability of the driving section during a period in which an inter-main-terminal voltage between the first main terminal and the second main terminal changes by a predetermined reference voltage difference owing to switching of the semiconductor device, compared with other at least some periods.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: April 4, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Seiki Igarashi
  • Publication number: 20220190706
    Abstract: A driving apparatus includes: a driving section configured to drive a control terminal of a semiconductor device according to a control signal input from an outside, the semiconductor device including a first main terminal, a second main terminal, and the control terminal that is configured to control a connection state between the first main terminal and the second main terminal that are connected in parallel with a snubber; and a drive control section configured to lower a drive capability of the driving section during a period in which an inter-main-terminal voltage between the first main terminal and the second main terminal changes by a predetermined reference voltage difference owing to switching of the semiconductor device, compared with other at least some periods.
    Type: Application
    Filed: October 26, 2021
    Publication date: June 16, 2022
    Inventor: Seiki IGARASHI
  • Publication number: 20220052608
    Abstract: An object of the present invention is to provide a semiconductor oscillation suppression circuit capable of suppressing voltage oscillation of a switching element with low loss. A semiconductor oscillation suppression circuit includes a wide-bandgap semiconductor element and a capacitor connected to the wide-bandgap semiconductor element in parallel and having a larger capacity than a junction capacitance of the wide-bandgap semiconductor element.
    Type: Application
    Filed: October 27, 2021
    Publication date: February 17, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Fumio YUKAWA, Seiki IGARASHI
  • Patent number: 10566966
    Abstract: A semiconductor device of the present invention suppresses high frequency noise caused in a semiconductor device incorporating SiC elements. The semiconductor device includes semiconductor elements connected in series, a SiC diode element connected in parallel to the semiconductor element, and an oscillation suppressing circuit being connected in parallel to the semiconductor element and the SiC diode element and suppressing voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element. The oscillation suppressing circuit suppresses voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element thereby improving reliability of the semiconductor device.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: February 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naotaka Matsuda, Seiki Igarashi, Hideaki Kakiki, Susumu Iwamoto
  • Publication number: 20180309438
    Abstract: A semiconductor device of the present invention suppresses high frequency noise caused in a semiconductor device incorporating SiC elements. The semiconductor device includes semiconductor elements connected in series, a SiC diode element connected in parallel to the semiconductor element, and an oscillation suppressing circuit being connected in parallel to the semiconductor element and the SiC diode element and suppressing voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element. The oscillation suppressing circuit suppresses voltage fluctuation caused in the SiC diode element in response to turn-ons of the semiconductor element thereby improving reliability of the semiconductor device.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Naotaka MATSUDA, Seiki IGARASHI, Hideaki KAKIKI, Susumu IWAMOTO
  • Patent number: 7433212
    Abstract: A system linking apparatus for generated electric power which may be made smaller and more efficient. The system linking apparatus is intended for connecting an electric power system to an output of a power generator through a linking inverter (PWM inverter). The system linking apparatus includes a magnetic energy regenerating circuit, a diode rectifier, and a capacitor. The magnetic energy regenerating circuit has a capacitor for condensing magnetic energy condensed in the power generator. The diode rectifier is connected with the magnetic energy regenerating circuit and operates to dc convert electric power generated by the power generator and output the converted power to the linking inverter. The capacitor is connected with the diode rectifier and operates to keep a dc output to the linking inverter at a predetermined voltage.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: October 7, 2008
    Assignees: Fuji Electric Device Technology Co., Ltd., Tokyo Institute of Technology
    Inventors: Seiki Igarashi, Yoshiyuki Uchida, Ryuichi Shimada
  • Publication number: 20060114696
    Abstract: A system linking apparatus for generated electric power which may be made smaller and more efficient. The system linking apparatus is intended for connecting an electric power system to an output of a power generator through a linking inverter (PWM inverter). The system linking apparatus includes a magnetic energy regenerating circuit, a diode rectifier, and a capacitor. The magnetic energy regenerating circuit has a capacitor for condensing magnetic energy condensed in the power generator. The diode rectifier is connected with the magnetic energy regenerating circuit and operates to dc convert electric power generated by the power generator and output the converted power to the linking inverter. The capacitor is connected with the diode rectifier and operates to keep a dc output to the linking inverter at a predetermined voltage.
    Type: Application
    Filed: October 26, 2005
    Publication date: June 1, 2006
    Applicants: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD., TOKYO INSTITUTE OF TECHNOLOGY
    Inventors: Seiki Igarashi, Yoshiyuki Uchida, Ryuichi Shimada
  • Patent number: 6657873
    Abstract: A switching power supply circuit reduces the capacity of the capacitor on the load side, reducing its size, weight, and cost. The switching power supply circuit has a pair of diodes connected in series, a pair of MOSFETs connected in series, a pair of capacitors connected in series, a snubber capacitor connected in parallel with the pair of diodes, the pair of MOSFETS, and the pair of capacitors. The circuit can include a pair of additional capacitors, connected respectively in parallel with the MOSFETS, to allow the MOSFETs to execute a zero-voltage switching. The circuit also includes an AC input terminal connected to the mutual connection point of the pair of diodes, a transformer including a primary winding having one end connected to the mutual connection point of the pair of MOSFETS, and the other end connected to the mutual connection point of the pair of capacitors. The primary winding has a center tap connected to another AC input terminal.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: December 2, 2003
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Seiki Igarashi
  • Publication number: 20030058664
    Abstract: A switching power supply circuit reduces the capacity of the capacitor on the load side, reducing its size, weight, and cost. The switching power supply circuit has a pair of diodes connected in series, a pair of MOSFETs connected in series, a pair of capacitors connected in series, a snubber capacitor connected in parallel with the pair of diodes, the pair of MOSFETS, and the pair of capacitors. The circuit can include a pair of additional capacitors, connected respectively in parallel with the MOSFETS, to allow the MOSFETs to execute a zero-voltage switching. The circuit also includes an AC input terminal connected to the mutual connection point of the pair of diodes, a transformer including a primary winding having one end connected to the mutual connection point of the pair of MOSFETS, and the other end connected to the mutual connection point of the pair of capacitors. The primary winding has a center tap connected to another AC input terminal.
    Type: Application
    Filed: August 23, 2002
    Publication date: March 27, 2003
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Seiki Igarashi
  • Patent number: 6459597
    Abstract: An electric power conversion apparatus includes a noise reduction device for reducing the common mode noise and the normal mode noise caused by on/off of the switching devices of an electric power conversion apparatus for driving an AC motor. Since the noise-compensation-current supply circuit of the noise reduction device uses devices with a lower breakdown voltage, the operating speed of the noise-compensation-current supply circuit is higher than the operating speed of the conventional noise-compensation-current supply circuit which uses devices with a higher breakdown voltage equivalent to the DC voltage of the electric power conversion apparatus.
    Type: Grant
    Filed: December 17, 2001
    Date of Patent: October 1, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiki Igarashi, Taichi Tanigawa
  • Publication number: 20020075702
    Abstract: An electric power conversion apparatus includes a noise reduction device for reducing the common mode noise and the normal mode noise caused by on/off of the switching devices of an electric power conversion apparatus for driving an AC motor. Since the noise-compensation-current supply circuit of the noise reduction device uses devices with a lower breakdown voltage, the operating speed of the noise-compensation-current supply circuit is higher than the operating speed of the conventional noise-compensation-current supply circuit which uses devices with a higher breakdown voltage equivalent to the DC voltage of the electric power conversion apparatus.
    Type: Application
    Filed: December 17, 2001
    Publication date: June 20, 2002
    Inventors: Seiki Igarashi, Taichi Tanigawa
  • Patent number: 6339262
    Abstract: A switching power supply uses zero-current and zero-voltage switching to reduce switching noise. A main switch and an auxiliary switch channel current and voltage between various component paths to maintain a DC output voltage while switching at zero-current or zero-voltage states. Switch ON-OFF time ratios are controlled with a simple scheme to improve the circuit power factor. The switching rate is set to arbitrary frequencies, with switch ON time and OFF time being controlled independently. Losses in efficiency when driving a load substantially less than the rated load are avoided. The switches and control functions can be implemented on an integrated circuit.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: January 15, 2002
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiki Igarashi, Akio Suzuki
  • Patent number: 6288595
    Abstract: A circuit accurately detects an arm voltage pulse from an inverter that is used for on-delay compensation. Specifically, switching elements S1 to S6 are provided with detection circuits C1 to C6, respectively, for detecting an on or off state of a corresponding inverter arm in order to detect an arm voltage pulse from the inverter accurately and without delay. Since outputs from the detection circuits C1, C3, C5 on an upper arm have an excessively high voltage level before processing, level-down circuits Dw1, Dw3, Dw5 reduce these outputs down to an appropriate voltage level for signals used by a control circuit. The outputs are then provided to an on-delay compensator in the control circuit.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: September 11, 2001
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Masaki Hirakata, Satoki Takizawa, Seiki Igarashi
  • Publication number: 20010019490
    Abstract: A switching power supply uses zero-current and zero-voltage switching to reduce switching noise. A main switch and an auxiliary switch channel current and voltage between various component paths to maintain a DC output voltage while switching at zero-current or zero-voltage states. Switch ON-OFF time ratios are controlled with a simple scheme to improve the circuit power factor. The switching rate is set to arbitrary frequencies, with switch ON time and OFF time being controlled independently. Conventional losses in efficiency when driving a load substantially less than the rated load are avoided. The switches and control functions can be implemented on an integrated circuit, reducing size and improving efficiency. Thus a flexible, simple design improves efficiency while reducing noise and manufacturing costs.
    Type: Application
    Filed: May 11, 2001
    Publication date: September 6, 2001
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Seiki Igarashi, Akio Suzuki
  • Patent number: 6111762
    Abstract: A switching power supply for outputting an isolated DC voltage includes a transformer TR1 having a secondary winding N21 and a tertiary winding N3; a semiconductor switch Q1; a DC voltage source (capacitor) C1 connected to the transformer TR1 and the semiconductor switch Q1; a rectifier D1 connected to the secondary winding N21; a power IC, the power supply voltage for which is obtained by rectifying the output of the tertiary winding N3 of the transformer TR1; and a comparator IC5 for detecting the voltage of the control power supply that is lower than a predetermined value, by which to shift to the power saving mode of operation. The above configuration eliminates the photo-coupler for transmitting the power saving signal and reduces the number of terminals of the power IC.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: August 29, 2000
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiki Igarashi, Akio Suzuki
  • Patent number: 6108218
    Abstract: A switching power supply for achieving a high power factor includes a rectifier Rect 1, a DC voltage source (capacitor) C1, a transformer TR1, a diode D6; a diode D7 a semiconductor switch Q1, and a inductor L1. The DC voltage source C1 is connected to an AC power supply AC via the rectifier Rect1. The transformer TR1 includes a primary winding N1, a secondary winding N2 and a tertiary winding N3. The transformer TR1 and the semiconductor switch Q1 are used to output an insulated DC voltage from the DC voltage source C1. The tertiary winding N3 is between the output of the rectifier Rect1 and the DC voltage source C1. The diodes D6 and D7 are connected to the respective input terminals of an AC power supply. The inductor L1 is connected between the output of the diodes D6, D7 and the semiconductor switch Q.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: August 22, 2000
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Seiki Igarashi, Akio Suzuki
  • Patent number: 6061253
    Abstract: A switching power supply uses zero-current and zero-voltage switching to reduce switching noise. A main switch and an auxiliary switch channel current and voltage between various component paths to maintain a DC output voltage while switching in zero-current or zero-voltage states. Switch ON-OFF time ratios are controlled with a simple scheme to improve the circuit power factor. The switching rate can be set to arbitrary frequencies, with switch ON time and OFF time being controlled independently. This scheme permits efficient driving of a load that is substantially less than the rated load, as generally found in portable TV circuits. The switches and control functions can be implemented on an integrated circuit.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: May 9, 2000
    Assignee: Fuji Electrical Co., Ltd.
    Inventors: Seiki Igarashi, Akio Suzuki