Patents by Inventor Seiko Netsu

Seiko Netsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250096749
    Abstract: A power amplifier circuit includes one or a plurality of amplification stages. A first amplification stage includes a first amplifier and a second amplifier that amplify a differential signal, a first capacitor electrically connected between an output terminal of the first amplifier and an input terminal of the second amplifier, a second capacitor electrically connected between an input terminal of the first amplifier and an output terminal of the second amplifier, a first resonant circuit and a first resistor that are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the first amplifier, and a second resonant circuit and a second resistor that are electrically connected in series with each other and are electrically connected between the output terminal and the input terminal of the second amplifier.
    Type: Application
    Filed: December 5, 2024
    Publication date: March 20, 2025
    Inventors: Seiko NETSU, Masatoshi HASE
  • Publication number: 20240396516
    Abstract: A balanced-to-unbalanced transformer circuit is formed with a transmission line including a main line and a sub-line which are coupled to each other. The main line comprises at least one wiring line. The sub-line comprises multiple wiring lines which are connected in parallel to one another and which are other than the at least one wiring line. Each of the wiring lines of the sub-line is coupled to the at least one wiring line of the main line.
    Type: Application
    Filed: August 1, 2024
    Publication date: November 28, 2024
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Seiko NETSU, Masatoshi HASE
  • Publication number: 20240388264
    Abstract: A Class E amplifier is configured to amplify a differential signal. Two output nodes of the Class E amplifier are connected to the power supply terminal with at least one choke inductor interposed therebetween. The Class E amplifier includes two transistors. The two transistors each includes a base or a gate connected to a corresponding one of two input nodes of the Class E amplifier and a collector or a drain connected to a corresponding one of the two output nodes of the Class E amplifier. First capacitors are each connected between the collector or the drain and an emitter or a source of a corresponding one of the two transistors. A first inductor is connected between the collector or the drain of one of the two transistors and the collector or the drain of the other of the two transistors.
    Type: Application
    Filed: July 26, 2024
    Publication date: November 21, 2024
    Inventors: Masatoshi HASE, Seiko NETSU
  • Patent number: 12119852
    Abstract: A first primary line has a first node at one end and a third node at another end and transmits a radio-frequency signal between the first node and the third node. A second primary line has a second node at one end and a fourth node at another end and transmits a radio-frequency signal between the second node and the fourth node. A first secondary line has a portion connected to the second node and is electromagnetically coupled to the first primary line. The second secondary line has a portion connected to the first node and has another end connected to a portion of the first secondary line. The second secondary line is electromagnetically coupled to the second primary line. A first capacitor is connected in parallel to a portion of the second primary line or a portion of the second secondary line.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: October 15, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Seiko Netsu, Masatoshi Hase
  • Publication number: 20240333231
    Abstract: A power amplifier circuit includes a distortion compensation amplifier circuit that includes a first amplifier that amplifies a first signal distributed from an input signal, and a second amplifier connected in parallel to the first amplifier, that amplifies a second signal distributed from the input signal and having a different phase from the first signal, and outputs an amplified signal obtained by combining a signal output from the first amplifier and the second amplifier, and an output amplifier circuit that outputs an output signal obtained by amplifying the amplified signal. The distortion compensation amplifier circuit further includes a control circuit that controls, based on power of the input signal, the first gain and the second gain to compensate for a change in a phase of the output amplifier circuit with respect to a change in the power of the signal input to the output amplifier circuit.
    Type: Application
    Filed: March 28, 2024
    Publication date: October 3, 2024
    Inventors: Masatoshi HASE, Seiko NETSU, Shingo YANAGIHARA
  • Publication number: 20240162870
    Abstract: A main line (transmission line) having a first end and a second end. A sub-line (transmission line) coupled to the main line. An unbalanced signal is input to and output from an unbalanced node connected to the first end. A balanced signal is input to and output from a first balanced node and a second balanced node. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. The second end and the third end are connected to a reference potential. The first balanced node and the second balanced node are connected to the unbalanced node and the fourth end, respectively. A first LC resonant circuit is connected between the second end and the reference potential or the third end and the reference potential.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Publication number: 20240162871
    Abstract: A main line (transmission line) has a first end and a second end. A sub-line (transmission line) coupled to the main line has a third end and a fourth end. The main line and the sub-line are coupled to each other. A direction of the main line is identical to a direction of the sub-line. An unbalanced node is connected to the first end. The first balanced node is connected to the first end, and the second balanced node is connected to the fourth end. The second end and the third end are connected to a reference potential. A first LC resonant circuit is connected between the first balanced node and the unbalanced node, the second balanced node and the fourth end, or the first end and the unbalanced node.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Publication number: 20240146271
    Abstract: A first transmission line transformer receives and outputs an unbalanced signal and performs impedance transformation. A second transmission line transformer performs unbalanced-to-balanced transformation. The first transmission line transformer includes a first main line and a first sub-line. The direction of the first main line is identical to the direction of the first sub-line. An end of the first sub-line is grounded. An end of the first main line is coupled to the unbalanced-signal input/output node. The second transmission line transformer includes a second main line and a second sub-line. The direction of the second main line is identical to a direction of the second sub-line. An end of the second main line and the second sub-line are grounded. An end of the second main line and the second sub-line are coupled to the balanced-signal input/output nodes.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 2, 2024
    Inventors: Masatoshi HASE, Koudai SUGIYAMA, Masamichi TOKUDA, Seiko NETSU
  • Publication number: 20220352914
    Abstract: A first primary line has a first node at one end and a third node at another end and transmits a radio-frequency signal between the first node and the third node. A second primary line has a second node at one end and a fourth node at another end and transmits a radio-frequency signal between the second node and the fourth node. A first secondary line has a portion connected to the second node and is electromagnetically coupled to the first primary line. The second secondary line has a portion connected to the first node and has another end connected to a portion of the first secondary line. The second secondary line is electromagnetically coupled to the second primary line. A first capacitor is connected in parallel to a portion of the second primary line or a portion of the second secondary line.
    Type: Application
    Filed: April 25, 2022
    Publication date: November 3, 2022
    Inventors: Seiko Netsu, Masatoshi Hase