Patents by Inventor Seiko Yoshida

Seiko Yoshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6333274
    Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: December 25, 2001
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation
    Inventors: Hiroyuki Akatsu, Soichi Nadahara, Takashi Nakao, Seiko Yoshida
  • Publication number: 20010023134
    Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.
    Type: Application
    Filed: March 31, 1998
    Publication date: September 20, 2001
    Inventors: HIROYUKI AKATSU, SOICHI NADAHARA, TAKASHI NAKAO, SEIKO YOSHIDA
  • Patent number: 6051885
    Abstract: A highly integrated semiconductor device is made using a high precision manufacturing process having a comparatively small number of process steps. The device is substantially free of misalignment between structures formed with respect to openings formed in the middle of layers. An interlayer insulating film with an opening is formed on a first conductor, and a second conductor is deposited on the resultant structure. Part of the second conductor enters the opening, thereby producing a depression in the second conductor, which has a sharp-angled bottom situated at the horizontal center of the opening. A film made of, for example, a nitride is deposited on the second conductor to fill the depression. Thereafter, this film is removed such that part of it remains in the depression. Using the remaining film as a mask, the second conductor is removed to the same level as the interlayer insulting film.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: April 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiko Yoshida
  • Patent number: 6046487
    Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.
    Type: Grant
    Filed: December 12, 1997
    Date of Patent: April 4, 2000
    Assignee: International Business Machines Corporation
    Inventors: John Preston Benedict, David Mark Dobuzinsky, Philip Lee Flaitz, Erwin N. Hammerl, Herbert Ho, James F. Moseman, Herbert Palm, Seiko Yoshida, Hiroshi Takato
  • Patent number: 5885863
    Abstract: A method for forming a contact is disclosed. A buried impurity region of a second conductivity type is formed in a semiconductor substrate of a first conductivity type. First and second well regions of a first and second conductivity types, respectively, are also formed in the semiconductor substrate. The second well region overlaps the first well region and contacts and surrounds the buried impurity region. A surface impurity concentration of the first well region is greater than a surface impurity concentration of the second well region. A contact to the second well region is formed.
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiko Yoshida
  • Patent number: 5763315
    Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: June 9, 1998
    Assignees: International Business Machines Corporation, Siemens Aktiengesellschaft, Kabushiki Kaisha Toshiba
    Inventors: John Preston Benedict, David Mark Dobuzinsky, Philip Lee Flaitz, Erwin N. Hammerl, Herbert Ho, James F. Moseman, Herbert Palm, Seiko Yoshida, Hiroshi Takato
  • Patent number: 5719072
    Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.
    Type: Grant
    Filed: July 11, 1995
    Date of Patent: February 17, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Sugiura, Hidehiro Watanabe, Seiko Yoshida
  • Patent number: 5486719
    Abstract: In a semiconductor device according to this invention, a first insulating film formed on only a pattern formation conductive film on a semiconductor substrate and having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness of the first insulating film is formed on the semiconductor substrate. A second insulating film having a reflectance which is 25% or more and periodically changes in accordance with a change in film thickness and having a refractive index different from that of the first insulating film is formed on only the first insulating film. A total reflectance of the first and second insulating films is less than 25%. A photosensitive film is formed on the second insulating film and exposed through a reticle to form a predetermined pattern. Etching is performed using the photosensitive film having this pattern to form a conductive pattern.
    Type: Grant
    Filed: April 14, 1994
    Date of Patent: January 23, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Souichi Sugiura, Hidehiro Watanabe, Seiko Yoshida