Patents by Inventor Seima UEZATO

Seima UEZATO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock signal stop detection circuit
    Patent number: 10033389
    Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: July 24, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Seima Uezato
  • CLOCK SIGNAL STOP DETECTION CIRCUIT
    Publication number: 20170288677
    Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
    Type: Application
    Filed: June 14, 2017
    Publication date: October 5, 2017
    Inventor: Seima UEZATO
  • Clock signal stop detection circuit
    Patent number: 9712173
    Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Seima Uezato
  • SEMICONDUCTOR DEVICE
    Publication number: 20170041006
    Abstract: A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state.
    Type: Application
    Filed: June 14, 2016
    Publication date: February 9, 2017
    Inventor: Seima UEZATO