Patents by Inventor Seiro Miyoshi

Seiro Miyoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10176290
    Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: January 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuro Urayama, Yoshihiro Yanai, Seiro Miyoshi
  • Publication number: 20170098029
    Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.
    Type: Application
    Filed: December 19, 2016
    Publication date: April 6, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takuro URAYAMA, Yoshihiro YANAI, Seiro MIYOSHI
  • Patent number: 9576100
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: February 21, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
  • Patent number: 9547743
    Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: January 17, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuro Urayama, Yoshihiro Yanai, Seiro Miyoshi
  • Publication number: 20160247679
    Abstract: According to one embodiment, stepped structure is formed on a semiconductor substrate, a processing film is formed to cover the stepped structure, a resist film is formed on the processing film in such a manner as to be thinner at a higher portion of the stepped structure than at a lower portion of the same, and the resist film and the processing film are etched to flatten the processing film.
    Type: Application
    Filed: June 5, 2015
    Publication date: August 25, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takuro URAYAMA, Yoshihiro Yanai, Seiro Miyoshi
  • Patent number: 9202763
    Abstract: According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 1, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro Miyoshi, Toshiyuki Aritake
  • Publication number: 20150220846
    Abstract: According to one embodiment, a process conversion difference in a processed pattern having undergone a process via the resist pattern can be predicted, based on results of simulation of a cross-sectional shape of the resist pattern by which predicted values of resist dimensions adapted to a relationship between a parameter for lithography and actual measurement values of the resist dimensions.
    Type: Application
    Filed: May 28, 2014
    Publication date: August 6, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ai INOUE, Minoru Inomoto, Kazuyuki Masukawa, Koutarou Sho, Seiro Miyoshi, Satoshi Usui
  • Patent number: 9070559
    Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 30, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiro Miyoshi, Maki Miyazaki, Kentaro Matsunaga
  • Publication number: 20150113485
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
  • Patent number: 8984454
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
  • Publication number: 20150031198
    Abstract: According to one embodiment, first, a core pattern is formed above a hard mask layer that is formed above a process object. Then, a spacer film is formed above the hard mask layer. Next, the spacer film is etch-backed. Subsequently, an embedded layer is embedded between the core patterns whose peripheral areas are surrounded by the spacer film. Then, the core pattern and the embedded layer are removed simultaneously. Subsequently, using the spacer pattern as a mask, the hard mask layer and the process object are processed.
    Type: Application
    Filed: March 4, 2014
    Publication date: January 29, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Seiro MIYOSHI, Maki MIYAZAKI, Kentaro MATSUNAGA
  • Publication number: 20140199792
    Abstract: According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result.
    Type: Application
    Filed: March 14, 2013
    Publication date: July 17, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro MIYOSHI, Toshiyuki ARITAKE
  • Patent number: 8759177
    Abstract: According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Yanai, Koichi Matsuno, Seiro Miyoshi
  • Publication number: 20140059502
    Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.
    Type: Application
    Filed: March 13, 2013
    Publication date: February 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
  • Publication number: 20130157437
    Abstract: According to one embodiment, firstly, an inversion pattern having a periodic pattern in which a first line pattern and a space are inversed and a non-periodic pattern arranged at an interval which is substantially equal to the width of the first line pattern from the end of the periodic pattern is formed above a processing object so as to correspond to the plurality of spaces between a plurality of first line patterns in a first pattern and the space between the first pattern and a second pattern. Next, a sidewall film is formed around the inversion pattern, and the periodic pattern is removed selectively. Thereafter, the processing object is etched using the sidewall pattern formed of the sidewall film and the non-periodic pattern surrounded by the sidewall film as masks.
    Type: Application
    Filed: August 31, 2012
    Publication date: June 20, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiro YANAI, Koichi MATSUNO, Seiro MIYOSHI
  • Patent number: 8423926
    Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Koshiba, Hidefumi Mukai, Seiro Miyoshi, Kazunori Iida
  • Publication number: 20120174045
    Abstract: According to one embodiment, an acceptance determining method of a blank for an EUV mask includes evaluating whether or not an integrated circuit device becomes defective, on the basis of information of a defect contained in a blank for an EUV mask and design information of a mask pattern to be formed on the blank. The integrated circuit device is to be manufactured by using the EUV mask. The EUV mask is manufactured by forming the mask pattern on the blank. And the blank is determined to be non-defective in a case that the integrated circuit device is not to be defective.
    Type: Application
    Filed: September 20, 2011
    Publication date: July 5, 2012
    Inventors: Takeshi KOSHIBA, Hidefumi Mukai, Seiro Miyoshi, Kazunori IIda
  • Patent number: 8178366
    Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: May 15, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Seiro Miyoshi, Hidefumi Mukai, Takeshi Koshiba
  • Publication number: 20110300646
    Abstract: In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value.
    Type: Application
    Filed: January 27, 2011
    Publication date: December 8, 2011
    Inventors: Seiro MIYOSHI, Hidefumi MUKAI, Takeshi KOSHIBA
  • Publication number: 20110224934
    Abstract: According to one embodiment, an evaluating apparatus includes a resist-pattern-data acquiring unit and an evaluating unit. The resist-pattern-data acquiring unit acquires resist pattern data having a plurality of feature values including at least two among a hole diameter measured concerning a pattern for hole formation in the resist pattern, an aspect ratio of the hole diameter, and a difference of hole diameters at a plurality of signal thresholds. The evaluating unit calculates an evaluation value using an evaluation function for evaluating whether a hole pattern formed on a processing target by using the pattern for hole formation is unopened and the resist pattern data and evaluates presence or absence of a risk that the hole pattern is unopened.
    Type: Application
    Filed: September 15, 2010
    Publication date: September 15, 2011
    Inventors: Seiro Miyoshi, Hideaki Abe, Kazuhiro Takahata, Masafumi Asano, Shoji Mimotogi, Tomoko Ojima, Masanari Kajiwara