Patents by Inventor Seishi Kobayashi

Seishi Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10721425
    Abstract: A solid-state imaging device in an embodiment is a solid-state imaging device including an output circuit configured to amplify signals read out from a plurality of pixels. The solid-state imaging device includes a logic circuit configured to generate operation timing of the output circuit and a delay generation circuit configured to control a delay amount for adjusting a pulse generated by the logic circuit to optimum timing. The delay generation circuit is configured of a first variable delay circuit configured to generate a delay pulse, a reference clock of which is delayed by a reference delay amount, a control circuit configured to control the first variable delay circuit and calculate, as a digital signal, a delay code corresponding to the reference delay amount, and a second variable delay circuit configured to adjust the timing of the pulse using the delay code.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 21, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Seishi Kobayashi, Kenji Hasegawa
  • Publication number: 20200059621
    Abstract: A solid-state imaging device in an embodiment is a solid-state imaging device including an output circuit configured to amplify signals read out from a plurality of pixels. The solid-state imaging device includes a logic circuit configured to generate operation timing of the output circuit and a delay generation circuit configured to control a delay amount for adjusting a pulse generated by the logic circuit to optimum timing. The delay generation circuit is configured of a first variable delay circuit configured to generate a delay pulse, a reference clock of which is delayed by a reference delay amount, a control circuit configured to control the first variable delay circuit and calculate, as a digital signal, a delay code corresponding to the reference delay amount, and a second variable delay circuit configured to adjust the timing of the pulse using the delay code.
    Type: Application
    Filed: February 15, 2019
    Publication date: February 20, 2020
    Inventors: Seishi Kobayashi, Kenji Hasegawa
  • Patent number: 10239263
    Abstract: A powder sintering lamination molding method which can improve the quality of the molded product without extending the time required for the lamination molding. A powder sintering lamination molding method, including the steps of, irradiating an irradiation region of the sliced layer of a molded product surrounded by an outline profile with a laser to selectively sinter the material powder of the material powder layer within the irradiation region; wherein a cooling period is provided after the laser is irradiated along the first line and before the laser is irradiated along the second line.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: March 26, 2019
    Assignee: Sodick Co., Ltd.
    Inventors: Ichiro Araie, Seishi Kobayashi, Yoshitaka Kato, Yasuyuki Miyashita
  • Publication number: 20160096325
    Abstract: A powder sintering lamination molding method which can improve the quality of the molded product without extending the time required for the lamination molding. A powder sintering lamination molding method, including the steps of, irradiating an irradiation region of the sliced layer of a molded product surrounded by an outline profile with a laser to selectively sinter the material powder of the material powder layer within the irradiation region; wherein a cooling period is provided after the laser is irradiated along the first line and before the laser is irradiated along the second line.
    Type: Application
    Filed: September 17, 2015
    Publication date: April 7, 2016
    Applicant: Sodick Co., Ltd.
    Inventors: Ichiro ARAIE, Seishi KOBAYASHI, Yoshitaka KATO, Yasuyuki MIYASHITA
  • Patent number: 5757447
    Abstract: A fluorescent lamp and a color liquid crystal display device, into which the fluorescent lamp is incorporated, use three-wavelength light emitting phosphers not to cause any interference fringe so as to eliminate color shadings from the display screen of said device. A phospher film consisting of a combination of the phosphers having their peak light emitting wavelengths at red, green and blue three-wavelength areas or ranges is formed on inner faces of a bulb of said fluorescent lamp, a half value width at the peak light emitting wavelength of each phospher i set to be in a range of 30 nm-100 nm, and a phospher defined by a general formula M.sub.3 (PO.sub.4).sub.2 :Sn, Mn (wherein M is at least one of Sr, Mg, Ba, Ca, Zn and Ga) is used as the red light emitting one. Fringes caused by the interference of light penetrating each optical component of the color liquid crystal display device with light reflected by front or boundary faces of these optical components can be thus prevented.
    Type: Grant
    Filed: December 1, 1995
    Date of Patent: May 26, 1998
    Assignees: Toshiba Lighting & Technology Corporation, Sharp Kabushiki Kaisha
    Inventors: Seishi Kobayashi, Akira Taya, Masanobu Okano