Abstract: An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and which is connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and which is connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. Each of the arithmetic processing units includes a pull data turn-back bus that propagates pull data read from its register file to the pull data bus.

Abstract: An arithmetic processing device includes arithmetic processing units, each having a calculator unit; a scheduler that controls a push instruction to write data to a register file in one of the arithmetic processing units and a pull instruction to read data from the register file; a pull request bus to which the scheduler outputs a pull request and are connected to the arithmetic processing units; a push request bus to which the scheduler outputs a push request and are connected to the arithmetic processing units; and a pull data bus that inputs, into the scheduler, pull data read from the register file in response to the pull request. The arithmetic processing unit includes a pull data turn-back bus that propagates the pull data read from the register file of the home calculator unit to the pull data bus.

Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Abstract: A processing device includes a cache memory to temporarily register data stored in the main memory and a registration circuit that, when registering the data stored in the main memory to the cache memory, acquires identification information set in association with an area in that the data to be registered is stored in the main memory, and registers, in the cache memory, the identification information together with the data to be registered. The processing device further includes a comparison circuit that, when executing an instruction to access the main memory, compares access information specified together with an address of an access destination and identification information registered together with access object data in the cache memory, with each other. The processing device yet further includes an access limitation circuit that stops execution of the instruction to access the main memory in accordance with a result of the comparison.

Abstract: It is provided an information processing system. A first processing unit instructs a second processing unit to update the state management information regarding first data managed by the second processing unit when the first processing unit accesses the first data and detects an error regarding the first data, the second processing unit issues a command for discarding the first data acquired by a processing unit other than the second processing unit to the processing unit other than the second processing unit, when the processing unit which acquires the first data receives the command, the processing unit which acquires the first data discards the first data and transmits a result of the discarding of the first data to the second processing unit, and the second processing unit updates the state management information regarding the first data based on the result received from the processing unit which acquires the first data.

Abstract: A node includes: an arithmetic processing device; and a first memory, wherein the arithmetic processing device includes: a processor core; a storing circuit to store a first failure node list in which first information indicating that a failure has occurred or second information indicating that no failure has occurred is set for each of nodes; a request issuing circuit to issue a first request to a second memory provided at a first node among the nodes; a setting circuit to set the first information for the first node in the first failure node list when the first request has timed out; and an issuance inhibition circuit to inhibit, based on a second request to the second memory from the processor core, the second request from being issued by the request issuing circuit when the first information is set for the first node in the first failure node list.

Abstract: An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Abstract: A data transmission apparatus includes a plurality of transmission data generation units that generate a first symbol by attaching one control bit to data of a predetermined bit length or a second symbol including data of a bit length longer than the predetermined bit length by one bit. The data transmission apparatus includes a transmission unit that transmits the first symbol or the second symbol generated by each of the transmission data generation units. At least one transmission data generation unit, in each timing at which the plurality of transmission data generation units generate the first symbol or the second symbol, generates the first symbol and the other transmission data generation units generate the second symbol.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: An information processing apparatus including a plurarity of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Abstract: An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Abstract: A node includes a first converting unit that performs conversion between a logical address and a physical address. The node includes a second converting unit that performs conversion between the physical address and processor identification information for identifying a processor included in a each of a plurality of nodes. The node includes a transmitting unit that transmits transmission data including the physical address and the processor identification information for accessing a storing area indicated by the physical address. The node includes a local determining unit that determines whether an access, indicated by the transmission data received from another nodes, is an access to a local area or an access to a shared area based on the physical address included in the transmission data received by the receiving unit.

Abstract: A data transfer method multiplexes a data character having a bit width M (M is a natural number greater than or equal to 3) and a control character having a bit width N (N is a natural number greater than or equal to 1), and adds a control character valid signal indicating whether the control character is valid, in order to generate a symbol code having a bit width M+1 or N+3, whichever is greater, and converts the symbol code from parallel data into serial data to be output to a transmission line.

Abstract: Address information of target data is stored in an ELA register at the start of a cache excluding process performed by BackEviction, and a request processing unit continuously re-executes a data acquiring process while an address of data requested to be acquired by a processor is present in the ELA register. The address information of the target data is stored in an EWB buffer at the start of autonomous move-out performed by a processor, and the cache excluding process performed by BackEviction is stopped when the address of data subjected to BackEviction is present in the EWB buffer.

Abstract: A cache-status maintaining unit stores address information of data stored in each entry of a cache memory, and maintains a status of each entry as any one of “strongly modified”, “weakly modified”, “shared”, and “Invalid”. A data-fetching-procedure selecting unit selects, upon receiving a data read request, at least one data fetching procedure based on the address information and the status. A read-data delivering unit selects latest data from among the data fetched, and delivers the latest data to a processor that issued the data read request. A cache-status updating unit updates, when registering the address information of the data, updates the status of the entry based on a type of the data read request.

Abstract: An information processing apparatus includes a plurality of computing units. At least one of the computing units includes a recording unit that records a status of an error occurrence in each of the computing units. The each of the computing units includes an error notifying unit that notifies the error occurrence to at least one of the computing units that includes the recording unit when an error occurs in the each of the computing units itself.

Abstract: In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.

Abstract: In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the request is retained halfway in the pipeline register in a pipeline processor, a first counter for counting the number of valid requests in the registers between a judgment section interposed in the pipeline register and for judging whether the request is a valid request and a request queue and a busy judgment section for judging whether the request queue is in a busy state based on the number of valid requests counted by the first counter are provided and a judgment is made by the judgment section based on the result of the busy state judgment by the busy judgment section.