Patents by Inventor SEISHI SANO

SEISHI SANO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and method for reading semiconductor memory device
    Patent number: 10726900
    Abstract: A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: July 28, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Seishi Sano
  • SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR READING SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180301180
    Abstract: A semiconductor memory device includes: a first bit line; a second bit line connected to the first bit line via a first switch; a charge transfer section including: a first holding section connected to the second bit line, the first holding section being configured to hold a readout voltage from a memory section that stores data, and a second holding section connected to the first bit line, the second holding section being configured to hold a voltage generated due to transfer of charges between the first holding section and the second holding section, the charge transfer section being configured to transfer charges between the first holding section and the second holding section via the first bit line; and a comparison section configured to compare a voltage held in the second holding section with a reference voltage.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 18, 2018
    Inventor: SEISHI SANO