Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: A phase shifter includes a substrate, waveguides and a wiring portion. The substrate includes optical waveguide regions and contact regions. Each contact region has contact portions. The waveguides are disposed at the substrate, and each of the waveguides accumulates carriers to modulate a phase of light for guiding propagation of the light. The wiring portion electrically connects each of the waveguides and each of the contact portions. Each of the contact portions connecting each of the waveguides to a corresponding one of electrodes to inject the carriers into each of the waveguides. Each of the waveguides has a lengthwise direction defined as a first direction, and a direction that is perpendicular to the first direction and is parallel to a surface of the substrate is defined as a second direction. The optical waveguide regions and the contact regions are disposed to be alternately aligned along the second direction.

Abstract: A semiconductor module may include a plurality of semiconductor elements; and a first power terminal, a second power terminal and a third power terminal electrically connected to the plurality of semiconductor elements. The plurality of semiconductor elements may include at least one upper arm switching element electrically connected between the first power terminal and the second power terminal; and at least one lower arm switching element electrically connected between the second power terminal and the third power terminal. A number of the at least one upper arm switching element may be different from a number of the at least one lower arm switching element.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: A semiconductor module may include a plurality of semiconductor elements; and a first power terminal, a second power terminal and a third power terminal electrically connected to the plurality of semiconductor elements. The plurality of semiconductor elements may include at least one upper arm switching element electrically connected between the first power terminal and the second power terminal; and at least one lower arm switching element electrically connected between the second power terminal and the third power terminal. A number of the at least one upper arm switching element may be different from a number of the at least one lower arm switching element.

Abstract: The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.

Abstract: A power module includes: a first insulating substrate including a first conductive layer; a first semiconductor device Q4 disposed on the first conductive layer 14D, the first semiconductor device of which one side of a main electrode is connected to the first conductive layer; a second insulating substrate disposed on the first insulating substrate so as to be opposite to the first semiconductor device and including a second conductive layer and a third conductive layer; a first pillar electrode connecting between the first conductive layer and the second conductive layer; and a second pillar electrode connecting between another side of the main electrode of the first semiconductor device and the third conductive layer. The second conductive layer is connected to any one of a positive or negative electrode pattern for supplying power to the first semiconductor device, and the third conductive layer is connected to another electrode pattern.

Abstract: A semiconductor device includes: a substrate; at least one semiconductor chip disposed on the substrate; a first resin layer disposed on the semiconductor chip, the first resin layer formed so as to cover the substrate and the semiconductor chip; a second resin layer disposed on the first resin layer, the second resin layer having a CTE smaller than a CTE of the first resin layer and having a coefficient of elasticity larger than a coefficient of elasticity of the first resin layer, wherein the second resin layer is formed so as to cover at least an upper surface of the first resin layer. There is provided the semiconductor device and a power module, capable of reducing a thermal resistance to improve a current density by reducing warpage of the semiconductor device, and capable of realizing cost reduction and miniaturization thereof by reducing the number of chips.

Abstract: The power module includes: a first metallic pattern; a plurality of power devices bonded on the first metallic pattern, each of the plurality of the power devices has a thickness thinner than a thickness of the metallic pattern; a frame member disposed so as to collectively enclose a predetermined number of the power devices on the first metallic pattern; a second metallic pattern disposed outside the frame member; and a resin layer configured to seal the plurality of the power devices and the first and second metallic patterns so as to include the frame member, wherein the frame member suppresses a stress according to a difference between a coefficient of thermal expansion of the metallic pattern and a coefficient of thermal expansion of the power devices. There is provided the power module easy to be fabricated, capable of suppressing the degradation of the bonded portion and improving reliability.

Abstract: The 2D-PC surface emitting laser includes: a PC layer; and a lattice point for forming resonant-state arranged in the photonic crystal layer, and configured so that a light wave in a band edge in photonic band structure in the PC layer is diffracted in a plane of the PC layer, and is diffracted in a surface vertical direction of the PC layer. The perturbation for diffracting the light wave in the surface vertical direction of the PC layer is applied to the lattice point for forming resonant-state. The term “perturbation” means that modulation is periodically applied to the lattice point for forming resonant-state. For example, the periodic modulation may be refractive index modulation, hole-diameter modulation, or hole-depth modulation.

Abstract: Provided is a two-dimensional photonic crystal surface emitting laser having an active layer for generating light of a predetermined wavelength range by an injection of electric current and a two-dimensional photonic crystal layer provided on one side of the active layer, the layer having a plate-shaped base member in which modified refractive index areas whose refractive index differs from that of the base member are arranged.

Abstract: The 2D-PC SEL includes: a PC layer; and a lattice point for forming resonant-state arranged in the PC layer, and configured so that a light wave at a band edge in photonic band structure in the PC layer is diffracted in a plane of the PC layer, and is diffracted in a direction normal to the surface of the PC layer. The lattice point for forming resonant-state has two types of lattice points including a first lattice point and a second lattice point, and the shapes of the adjacent first lattice point and second lattice point are different from each other.

Abstract: The 2D-PC vertical cavity surface emitting laser includes: a PC layer; and a lattice point for forming resonant-state arranged in the photonic crystal layer, and configured so that a light wave in a band edge in photonic band structure in the PC layer is diffracted in a plane of the PC layer, and is diffracted in a surface vertical direction of the PC layer. The perturbation for diffracting the light wave in the surface vertical direction of the PC layer is applied to the lattice point for forming resonant-state. The term “perturbation” means that modulation is periodically applied to the lattice point for forming resonant-state. For example, the periodic modulation may be refractive index modulation, hole-diameter modulation, or hole-depth modulation.

Abstract: A photonic crystal surface emission laser includes an active layer, and a photonic crystal layer made of a plate-shaped slab provided with modified refractive index area having a refractive index different from that of the slab, the modified refractive index areas being arranged on each of the lattice points of a first rhombic-like lattice and a second rhombic-like lattice in which both diagonals are mutually parallel and only one diagonal is of a different length, wherein ax1, ax2, ay, and n satisfy the following inequality: ? 1 a x ? ? 1 - 1 a x ? ? 2 ? ( 1 a x ? ? 1 + 1 a x ? ? 2 ) 2 + ( 2 a y ) 2 ? 1 n .

Abstract: Provided is a two-dimensional photonic crystal surface emitting laser having an active layer for generating light of a predetermined wavelength range by an injection of electric current and a two-dimensional photonic crystal layer provided on one side of the active layer, the layer having a plate-shaped base member in which modified refractive index areas whose refractive index differs from that of the base member are arranged.

Abstract: A photonic crystal surface emission laser includes an active layer, and a photonic crystal layer made of a plate-shaped slab provided with modified refractive index area having a refractive index different from that of the slab, the modified refractive index areas being arranged on each of the lattice points of a first rhombic-like lattice and a second rhombic-like lattice in which both diagonals are mutually parallel and only one diagonal is of a different length, wherein ax1, ax2, ay, and n satisfy the following inequality: ? 1 a x ? ? 1 - 1 a x ? ? 2 ? ( 1 a x ? ? 1 + 1 a x ? ? 2 ) 2 + ( 2 a y ) 2 ? 1 n .