Patents by Inventor Seiya Ichimori

Seiya Ichimori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130332928
    Abstract: There is provided an information processing system including circuitry that acquires application definition information that defines a module used by an application, rewrites the application definition information depending on a circumstance of a device in which a process of the application is executed, and provides the rewritten application definition information to the device in which the process is executed.
    Type: Application
    Filed: May 22, 2013
    Publication date: December 12, 2013
    Applicant: Sony Corporation
    Inventors: Hiroaki Ishizawa, Seiya Ichimori
  • Publication number: 20130332686
    Abstract: A computer-implemented information processing method, apparatus and computer-readable storage medium comprising computer-executable instructions that, when executed by at least one processor, perform an information processing method. Configuration management information is rewritten base based on a status of a first apparatus designated to execute a process. The configuration management information defines one or more relationships between one or more virtual devices and one or more physical devices. The rewritten configuration management information is provided to the first apparatus.
    Type: Application
    Filed: May 22, 2013
    Publication date: December 12, 2013
    Applicant: Sony Corporation
    Inventors: Hiroaki Ishizawa, Seiya Ichimori
  • Publication number: 20120297151
    Abstract: If it is determined in step S51 that allocation for an instruction part has been requested and it is determined in step S52 that a memory use amount of an instruction part of an allocation target program exceeds an upper limit, a memory area that is being used by the instruction part of the allocation target program is released in step S53 and memory allocation for the instruction part is performed in step S54. If it is determined in step S52 that the memory use amount of the instruction part of the allocation target program does not exceed the upper limit, the process in step S53 is skipped. If it is determined in step S51 that allocation for a data part is requested, a normal memory allocation process is performed in step S55. The present disclosure may be applied to, for example, an embedded device.
    Type: Application
    Filed: May 7, 2012
    Publication date: November 22, 2012
    Inventors: Hiroki KAMINAGA, Seiya Ichimori, Katsuya Takahashi, Yoriko Komatsuzaki, Masahiro Tamori
  • Patent number: 8205033
    Abstract: A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: June 19, 2012
    Assignee: Sony Corporation
    Inventors: Shusuke Saeki, Satoru Iwasaki, Seiya Ichimori, Hiroki Nagahama, Kazumi Sato
  • Publication number: 20090119450
    Abstract: A memory device includes a non-volatile memory which allows data to be written, read, and erased electrically and in which writing and reading are done in units of a page and erasing is done in units of a block including a plurality of pages, and a control section that manages access to the non-volatile memory. The control section performs management of access to the non-volatile memory by performing logical address-physical address translation (logical-physical translation) in translation units (TUs) each being an integer fraction of a size of the block and an integer multiple of a page size.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 7, 2009
    Inventors: Shusuke SAEKI, Satoru Iwasaki, Seiya Ichimori, Hiroki Nagahama, Kazumi Sato