Patents by Inventor Seiya Isozaki
Seiya Isozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11387172Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.Type: GrantFiled: February 21, 2019Date of Patent: July 12, 2022Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yoshinori Deguchi, Iwao Natori, Seiya Isozaki
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Patent number: 11211349Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.Type: GrantFiled: June 24, 2020Date of Patent: December 28, 2021Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Seiya Isozaki, Tatsuya Kobayashi, Kota Jinno
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Publication number: 20210057361Abstract: A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.Type: ApplicationFiled: June 24, 2020Publication date: February 25, 2021Inventors: Seiya ISOZAKI, Tatsuya KOBAYASHI, Kota JINNO
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Publication number: 20190295930Abstract: A pad is formed on an interlayer insulating film, art insulating film is formed on the interlayer insulating film to cover the pad, and an opening portion exposing a part of the pad is formed in the insulating film. A metal film electrically connected to the pad is formed on the pad exposed from the opening portion and on the insulating film. The metal film integrally includes a first portion on the pad exposed from the opening portion and a second portion on the insulating film. An upper surface of the metal film has a wire bonding region for bonding a wire to the metal film and a probe contact region for bringing the probe into contact with the metal film, the wire bonding region is located on the first portion of the metal film, and the probe contact region is located on the second portion of the metal film.Type: ApplicationFiled: February 21, 2019Publication date: September 26, 2019Inventors: Yoshinori DEGUCHI, Iwao NATORI, Seiya ISOZAKI
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Patent number: 10347604Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.Type: GrantFiled: February 21, 2018Date of Patent: July 9, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuki Yagyu, Seiya Isozaki
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Patent number: 10181450Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.Type: GrantFiled: February 1, 2017Date of Patent: January 15, 2019Assignee: Renesas Electronics CorporationInventors: Seiya Isozaki, Takashi Moriyama, Takehiko Maeda
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Publication number: 20180277511Abstract: To provide a semiconductor device having improved reliability. A method of manufacturing the semiconductor device includes connecting a wire comprised of copper with a conductive layer formed on the pad electrode of a semiconductor chip, heat treating the semiconductor chip, and then sealing the semiconductor chip and the wire with a resin.Type: ApplicationFiled: February 21, 2018Publication date: September 27, 2018Applicant: Renesas Electronics CorporationInventors: Yuki YAGYU, Seiya ISOZAKI
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Publication number: 20170287868Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.Type: ApplicationFiled: February 1, 2017Publication date: October 5, 2017Inventors: Seiya ISOZAKI, Takashi MORIYAMA, Takehiko MAEDA
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Patent number: 7994614Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.Type: GrantFiled: March 18, 2009Date of Patent: August 9, 2011Assignee: Renesas Electronics CorporationInventors: Kouji Tanaka, Seiya Isozaki
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Publication number: 20090243044Abstract: Provided is a semiconductor wafer with a scribe line region and a plurality of element forming regions partitioned by the scribe line region, the semiconductor wafer including: conductive patterns formed in the scribe line region; and an island-shaped passivation film formed above at least a conductive pattern, which is or may be exposed to a side surface of a semiconductor chip obtained by dicing the semiconductor wafer along the scribe line region, among the conductive patterns, so that the island-shaped passivation film is opposed to the conductive pattern.Type: ApplicationFiled: March 18, 2009Publication date: October 1, 2009Applicant: NEC Electronics CorporationInventors: Kouji Tanaka, Seiya Isozaki
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Patent number: 6608384Abstract: A semiconductor device includes a bonding-structure for electrically and mechanically bonding a solder ball to the electrode pad. The bonding-structure includes flexible arms that are connected to a common supporting layer that allows a relative displacement of the solder ball in relation to the semiconductor chip. The arms extending in one direction are supported by one supporting layer and the arms extending in an opposite direction are supported by another supporting layer.Type: GrantFiled: August 3, 2001Date of Patent: August 19, 2003Assignee: Nec CorporationInventor: Seiya Isozaki
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Patent number: 6400034Abstract: A semiconductor device allowing a finer terminal pitch, a low profile, and easy product inspection is disclosed. A semiconductor device includes a semiconductor chip and a film substrate having the semiconductor chip connected thereon. The film substrate includes an insulating film having a plurality of openings formed in a desired pattern and a wiring layer formed in a chip-connecting surface of the insulating film. Solder balls are each directly bonded to the external connection pads through the openings. The wiring layer includes substrate pads each being connected to the chip pads of the semiconductor chip, and external connection pads each being electrically connected to these substrate pads. The external connection pads are each formed over the openings so that the openings are covered with the external connection pads on the chip-connecting surface of the insulating film, respectively.Type: GrantFiled: July 12, 2000Date of Patent: June 4, 2002Assignee: NEC CorporationInventors: Takehiro Kimura, Seiya Isozaki
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Publication number: 20020017725Abstract: The present invention provides a semiconductor device comprising: a semiconductor chip having at least an electrode pad; at least a solder material; and at least a bonding-structure for electrically and mechanically bonding the solder material to the electrode pad, wherein the bonding-structure has a flexibility and allows a relative displacement of the solder material in relation to the semiconductor chip.Type: ApplicationFiled: August 3, 2001Publication date: February 14, 2002Applicant: NEC CorporationInventor: Seiya Isozaki
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Patent number: 5610440Abstract: In a semiconductor device comprising a semiconductor chip, a heat radiation plate mounting the semiconductor chip thereon and having a plurality of rounded corner portions of a first radius, a ceramic substrate for mounting the heat radiation plate, and a metallize pattern formed onto the ceramic substrate for soldering the heat radiation plate onto the ceramic substrate, the metallize pattern has a plurality of rounded corner portions of a second radius. The metallize pattern is larger than the heat radiation plate in area. The first radius is greater than the second radius.Type: GrantFiled: February 23, 1996Date of Patent: March 11, 1997Assignee: NEC CorporationInventor: Seiya Isozaki