Patents by Inventor Seiya Kasai

Seiya Kasai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230289505
    Abstract: A solution-searching system encompasses an output adjustment unit having N signal adjustment circuits for converting provisional output-adjustment signals into final output-adjustment signals, 2N data generation units for generating binary data, 2N data conversion units which convert the binary data into information, a fluctuation setting unit for suppling bias probabilities to the signal adjustment circuits, fluctuation probabilities to the data generation units, and threshold values to the data conversion units, setting occurrence-frequencies of the binary data for making an occurrence-frequency of a specific variable, and a feedback control unit for determining whether an optimal solution has been found based on the information converted by the data conversion units and search-problem information preliminarily entered, by repeating transmission of the final output-adjustment signals to the output adjustment units, if the optimal solution has not been found.
    Type: Application
    Filed: April 27, 2023
    Publication date: September 14, 2023
    Inventors: Masashi AONO, Seiya KASAI, Kaori OHKODA, Shingo FUKUDA
  • Publication number: 20220239293
    Abstract: A pulse generator encompasses an output circuit connected between a higher-potential power-supply and a lower-potential power-supply, and a voltage source for supplying an input voltage to the output circuit. The output circuit is implemented by a resistor-connected complementary transistor-circuit including a CMOS inverter, and a resistive element connected in series to the CMOS inverter, and the input voltage swings in a span including at least a simultaneous-conduction regime of the CMOS inverter, with respect to a swing-center potential set to an inverter threshold as a reference. A resistance value of the resistive element is selected such that a potential drop by the shoot-through current when the maximum value of the shoot-through current flows through the resistive element provide a deviation of the input voltage from the simultaneous-conduction regime.
    Type: Application
    Filed: January 24, 2022
    Publication date: July 28, 2022
    Inventors: Seiya KASAI, Naoki SUEFUJI
  • Patent number: 9287962
    Abstract: A signal reproduction apparatus reproduces, from an input signal containing a weak signal which is a piece of transmission information and noise superimposed thereon, the weak signal through use of a stochastic resonance phenomenon. The apparatus includes N nonlinear elements NL1-NLN (N is a natural number equal to or greater than 2) which receive N reception signals R (split signals) split to N branch lines L1-LN, and output nonlinear output signals NLO1-NLON; N delay elements D1-DN which delay the nonlinear output signals by different times, respectively; and a combiner which combines delay signals DS1-DSN output from the delay elements D1-DN. The correlation among the noise components contained in the delay signals DS1-DSN obtained by delaying the nonlinear output signal is extremely small, and the correlation of the weak signal is large.
    Type: Grant
    Filed: December 17, 2012
    Date of Patent: March 15, 2016
    Assignee: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Seiya Kasai, Yukihiro Tadokoro, Akihisa Ichiki
  • Publication number: 20150207557
    Abstract: A signal reproduction apparatus reproduces, from an input signal containing a weak signal which is a piece of transmission information and noise superimposed thereon, the weak signal through use of a stochastic resonance phenomenon. The apparatus includes N nonlinear elements NL1-NLN (N is a natural number equal to or greater than 2) which receive N reception signals R (split signals) split to N branch lines L1-LN, and output nonlinear output signals NLO1-NLON; N delay elements D1-DN which delay the nonlinear output signals by different times, respectively; and a combiner which combines delay signals DS1-DSN output from the delay elements D1-DN. The correlation among the noise components contained in the delay signals DS1-DSN obtained by delaying the nonlinear output signal is extremely small, and the correlation of the weak signal is large.
    Type: Application
    Filed: December 17, 2012
    Publication date: July 23, 2015
    Applicant: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
    Inventors: Seiya Kasai, Yukihiro Tadokoro, Akihisa Ichiki
  • Patent number: 8314646
    Abstract: The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: November 20, 2012
    Assignee: Japan Science and Technology Agency
    Inventor: Seiya Kasai
  • Publication number: 20110050332
    Abstract: The purpose is to detect minute electrical signals embedded in noise with a simple device configuration and easily reduce the area of the device by utilizing a semiconductor device in particular. This signal reproducing device (1) includes: N FETs (61 to 6N) each receiving a common input signal (VIN) at a gate terminal and having a bias voltage (VDD) applied to a drain terminal; and an adder circuit (4) connected to source terminals of the FETs (61 to 6N), for combining currents between the drain terminals and the source terminals of the FETs (61 to 6N) and outputting the resulting current, wherein the FETs (61 to 6N) and the bias voltage (VDD) are set so that a voltage at the gate terminal having the common input signal (VIN) applied thereto falls within a subthreshold region of voltages less than a threshold voltage of the FETs (61 to 6N).
    Type: Application
    Filed: September 2, 2008
    Publication date: March 3, 2011
    Inventor: Seiya Kasai