Patents by Inventor Seiya KAWAMORITA

Seiya KAWAMORITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105139
    Abstract: Provided is a display device including gate drive circuits, a signal line connected to the gate drive circuit, a signal line connected to the gate drive circuit, a gate terminal, inspection terminals, and a connection line. The connection line connects the signal line and the signal line. The inspection terminal is disposed on the signal line. The inspection terminal is disposed on the signal line. The inspection terminals are terminals input with an inspection signal at the time of inspection.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 28, 2024
    Inventors: Satoshi HORIUCHI, Akane SUGISAKA, Seiya KAWAMORITA, Shinji MATSUBARA
  • Patent number: 11552109
    Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.
    Type: Grant
    Filed: January 19, 2021
    Date of Patent: January 10, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Asai, Satoshi Horiuchi, Seiya Kawamorita, Shinji Matsubara, Seijirou Gyouten
  • Patent number: 11150706
    Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: October 19, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Satoshi Horiuchi, Seijirou Gyouten, Yoshihiro Asai, Seiya Kawamorita
  • Publication number: 20210225879
    Abstract: A circuit substrate includes a substrate portion having a variable-external-shape portion; a circuit portion, having a configuration in which circuit blocks adjacent to each other in a first direction; a plurality of trunk wiring lines bent along the circuit blocks displaced with respect to each other in a second direction; and a plurality of branch wiring lines, wherein the plurality of trunk wiring lines include a first trunk wiring line and a second trunk wiring line, and among the plurality of branch wiring lines, a plurality of branch wiring lines connected to a plurality of unit circuits constituting a center-side circuit block include at least a first branch wiring line connected to the first trunk wiring line and a second branch wiring line connected to the second trunk wiring line and disposed farther than the first branch wiring line from a end-side circuit block in the first direction.
    Type: Application
    Filed: January 19, 2021
    Publication date: July 22, 2021
    Inventors: Yoshihiro ASAI, Satoshi HORIUCHI, Seiya KAWAMORITA, Shinji MATSUBARA, Seijirou GYOUTEN
  • Publication number: 20200379523
    Abstract: A plurality of circuit portions include a central side circuit portion connected to at least a central side-wiring line lead-out portion among a plurality of wiring line lead-out portions, and an end side circuit portion that is connected to at least an end side-wiring line lead-out portion among the plurality of wiring line lead-out portions, is also located on an end side in a first direction being an extending direction of a central side-outer shape portion having a linear shape with respect to the central side circuit portion, and is configured such that a dimension in a second direction being a direction in which the plurality of circuit portions and a central side region are aligned is smaller than that of the central side circuit portion.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 3, 2020
    Inventors: Satoshi HORIUCHI, Seijirou GYOUTEN, Yoshihiro ASAI, Seiya KAWAMORITA