Patents by Inventor Seiya SUGIMACHI
Seiya SUGIMACHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240136399Abstract: The object is to provide a technology that can shorten a routing length of a gate wire connecting a control IC that controls driving first and second semiconductor elements that are connected in parallel with each other, to a gate pad of one of the first and second semiconductor elements disposed distant from the control IC. A first semiconductor element and a second semiconductor element are disposed so that a long side of the first semiconductor element faces a side of the second semiconductor element, and a HVIC or a LVIC, the first semiconductor element, and the second semiconductor element are disposed in this order in a direction orthogonal to a first direction, the gate pad is disposed on the first semiconductor element on one side in the first direction, and the gate pad is disposed on the second semiconductor element on the other side in the first direction.Type: ApplicationFiled: August 16, 2023Publication date: April 25, 2024Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Kazufumi OKI, Okinori INOUE, Kazuhiro KAWAHARA, Kosuke YAMAGUCHI
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Patent number: 11710683Abstract: A semiconductor module includes: a switching device including a gate pad; an output unit including an output pad connected with the gate pad of the switching device through a wire and outputting a drive signal from the output pad to the switching device; a temperature protection circuit detecting temperature and performing protection operation; and a heat conduction pattern connected with the output pad, extending from the output pad toward the temperature protection circuit, and conducting heat generated at the switching device to the temperature protection circuit.Type: GrantFiled: July 9, 2021Date of Patent: July 25, 2023Assignee: Mitsubishi Electric CorporationInventors: Seiya Sugimachi, Kazufumi Oki
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Publication number: 20220208663Abstract: A semiconductor module includes: a switching device including a gate pad; an output unit including an output pad connected with the gate pad of the switching device through a wire and outputting a drive signal from the output pad to the switching device; a temperature protection circuit detecting temperature and performing protection operation; and a heat conduction pattern connected with the output pad, extending from the output pad toward the temperature protection circuit, and conducting heat generated at the switching device to the temperature protection circuit.Type: ApplicationFiled: July 9, 2021Publication date: June 30, 2022Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Kazufumi OKI
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Patent number: 11322432Abstract: A semiconductor module includes: an insulating heat dissipation sheet; a semiconductor device provided on the heat dissipation sheet; a lead frame including a lead terminal and a die pad which are formed integrally; a wire connecting the lead frame to the semiconductor device and constituting a main current path; and a mold resin scaling the heat dissipation sheet, the semiconductor device, the lead frame and the wire, wherein the lead terminal is led out from the mold resin, the heat dissipation sheet is in direct contact with an undersurface of the die pad, and the wire is bonded to the die pad directly above a contact part provided between the die pad and the heat dissipation sheet.Type: GrantFiled: April 24, 2020Date of Patent: May 3, 2022Assignee: Mitsubishi Electric CorporationInventors: Seiya Sugimachi, Shinji Sakai
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Patent number: 11302569Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of (a) preparing a lead frame including a power chip die pad to which two terminals are connected, a control element die pad to which one terminal is connected, and tie bar portions connecting between a plurality of terminals including the two terminals, (b) placing a power chip and a free wheel diode on the power chip die pad and placing ICs on the control element die pad, (c) encapsulating in a mold resin to allow the tie bar portions to be exposed outside and a plurality of terminals including the two terminals and the one terminal to protrude outward, and (d) removing the tie bar portions other than the tie bar portions connecting the two terminals.Type: GrantFiled: December 16, 2019Date of Patent: April 12, 2022Assignee: Mitsubishi Electric CorporationInventors: Shuhei Yokoyama, Seiya Sugimachi, Maki Hasegawa, Kosuke Yamaguchi, Shogo Shibata
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Patent number: 11251178Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.Type: GrantFiled: August 22, 2019Date of Patent: February 15, 2022Assignee: Mitsubishi Electric CorporationInventors: Seiya Sugimachi, Masataka Shiramizu
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Publication number: 20210125904Abstract: A semiconductor module includes: an insulating heat dissipation sheet; a semiconductor device provided on the heat dissipation sheet; a lead frame including a lead terminal and a die pad which are formed integrally; a wire connecting the lead frame to the semiconductor device and constituting a main current path; and a mold resin scaling the heat dissipation sheet, the semiconductor device, the lead frame and the wire, wherein the lead terminal is led out from the mold resin, the heat dissipation sheet is in direct contact with an undersurface of the die pad, and the wire is bonded to the die pad directly above a contact part provided between the die pad and the heat dissipation sheet.Type: ApplicationFiled: April 24, 2020Publication date: April 29, 2021Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Shinji SAKAI
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Publication number: 20200303237Abstract: A method for manufacturing a semiconductor device according to the present invention includes the steps of (a) preparing a lead frame including a power chip die pad to which two terminals are connected, a control element die pad to which one terminal is connected, and tie bar portions connecting between a plurality of terminals including the two terminals, (b) placing a power chip and a free wheel diode on the power chip die pad and placing ICs on the control element die pad, (c) encapsulating in a mold resin to allow the tie bar portions to be exposed outside and a plurality of terminals including the two terminals and the one terminal to protrude outward, and (d) removing the tie bar portions other than the tie bar portions connecting the two terminals.Type: ApplicationFiled: December 16, 2019Publication date: September 24, 2020Applicant: Mitsubishi Electric CorporationInventors: Shuhei YOKOYAMA, Seiya SUGIMACHI, Maki HASEGAWA, Kosuke YAMAGUCHI, Shogo SHIBATA
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Publication number: 20190378835Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Masataka SHIRAMIZU
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Patent number: 10461073Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.Type: GrantFiled: November 3, 2016Date of Patent: October 29, 2019Assignee: Mitsubishi Electric CorporationInventors: Seiya Sugimachi, Masataka Shiramizu
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Patent number: 10229869Abstract: A semiconductor device has a configuration in which a high-side module portion and a low-side module portion overlap each other. The semiconductor device further includes a control-side frame extending across the high-side module portion and the low-side module portion, and having a high-side integrated circuit and a low-side integrated circuit placed thereon. The high-side integrated circuit of the high-side module portion and the low-side integrated circuit of the low-side module portion are placed on one main surface of the control-side frame. At a boundary between the high-side module portion and the low-side module portion, the control-side frame is bent such that the high-side semiconductor chip and the low-side semiconductor chip face each other.Type: GrantFiled: August 30, 2017Date of Patent: March 12, 2019Assignee: Mitsubishi Electric CorporationInventors: Seiya Sugimachi, Masataka Shiramizu
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Publication number: 20180158761Abstract: A semiconductor device has a configuration in which a high-side module portion and a low-side module portion overlap each other. The semiconductor device further includes a control-side frame extending across the high-side module portion and the low-side module portion, and having a high-side integrated circuit and a low-side integrated circuit placed thereon. The high-side integrated circuit of the high-side module portion and the low-side integrated circuit of the low-side module portion are placed on one main surface of the control-side frame. At a boundary between the high-side module portion and the low-side module portion, the control-side frame is bent such that the high-side semiconductor chip and the low-side semiconductor chip face each other.Type: ApplicationFiled: August 30, 2017Publication date: June 7, 2018Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Masataka SHIRAMIZU
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Publication number: 20170207213Abstract: A power module includes a first MOS transistor and a first Schottky barrier diode for a lower arm, and a second MOS transistor and a second Schottky barrier diode for an upper arm. In one embodiment, one positive-side power supply terminal and one negative-side power supply terminal are provided, while an output terminal to which the first and second MOS transistors are connected and an output terminal to which the first and second Schottky barrier diodes are connected are provided as separate output terminals.Type: ApplicationFiled: November 3, 2016Publication date: July 20, 2017Applicant: Mitsubishi Electric CorporationInventors: Seiya SUGIMACHI, Masataka SHIRAMIZU