Abstract: An internal clock signal, of which a pulse repetition period is half of that of an external clock signal, is produced in a test circuit from the external clock signal and an external clock enabling signal of which a phase is shifted from that of the external clock signal by ¼ of the pulse repetition period of the external clock signal. When an external write command signal set to a low level is received in the test circuit, an internal write command signal, of which a level is risen up in synchronization with a leading edge of the external clock signal, is produced, and a first pre-charge signal, of which a level is risen up in synchronization with a trailing edge of the internal clock signal obtained just after the leading edge of the external clock signal, is produced. Therefore a write recovery time-period equal to ¼ of the pulse repetition period of the external clock signal is obtained from the internal write command signal and the first pre-charge signal.