Patents by Inventor Seizuo Kakimoto

Seizuo Kakimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030230784
    Abstract: A semiconductor device of the present invention includes: a semiconductor substrate; a deep well region of a first conductivity type, formed in the semiconductor substrate; a plurality of shallow well regions of a second conductivity type, formed in the deep well region; a source region and a drain region of the first conductivity type, respectively formed in the plurality of shallow well regions; a channel region formed between the source region and the drain region; a gate insulating film formed on the channel region; and a gate electrode formed on the gate insulating film, wherein the gate electrode is electrically connected to a corresponding one of the shallow well regions, and the shallow well region is electrically separated from the adjacent shallow well region.
    Type: Application
    Filed: May 15, 2003
    Publication date: December 18, 2003
    Inventors: Hiroshi Iwata, Seizuo Kakimoto, Masayuki Nakano, Toshimasa Matsuoka