Patents by Inventor Sejal Chheda

Sejal Chheda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for adding features to a design layout and process for designing a mask
    Patent number: 6593226
    Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).
    Type: Grant
    Filed: July 17, 2001
    Date of Patent: July 15, 2003
    Assignee: Motorola, Inc.
    Inventors: Edward O. Travis, Aykut Dengi, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton, Ruiqi Tian, Robert E. Boone, Alfred J. Reich
  • Semiconductor device and a process for designing a mask
    Patent number: 6396158
    Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: May 28, 2002
    Assignee: Motorola Inc.
    Inventors: Edward O. Travis, Aykut Dengi, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton, Ruiqi Tian
  • Method for adding features to a design layout and process for designing a mask
    Publication number: 20020050655
    Abstract: Selective placement of polishing dummy feature patterns, rather than indiscriminate placement of polishing dummy feature patterns, is used. Both low frequency (hundreds of microns and larger) and high frequency (10 microns and less) of topography changes are examined. The polishing dummy feature patterns can be specifically tailored to a semiconductor device and polishing conditions used in forming the semiconductor device. When designing an integrated circuit, polishing effects for the active features can be predicted. After polishing dummy feature pattern(s) are placed into the layout, the planarity can be examined on a local level (a portion but not all of the device) and a more global level (all of the device, devices corresponding to a reticle field, or even an entire wafer).
    Type: Application
    Filed: July 17, 2001
    Publication date: May 2, 2002
    Inventors: Edward O. Travis, Aykut Dengi, Sejal Chheda, Tat-Kwan Yu, Mark S. Roberton, Ruiqi Tian, Robert E. Boone, Alfred J. Reich