Patents by Inventor Sejie TAKAKI
Sejie TAKAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240040793Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.Type: ApplicationFiled: October 12, 2023Publication date: February 1, 2024Inventors: SEJIE TAKAKI, Joonhee Lee
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Patent number: 11856773Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure.Type: GrantFiled: February 16, 2021Date of Patent: December 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yujin Seo, Euntaek Jung, Byoungil Lee, Seul Lee, Joonhee Lee, Changdae Jung, Bonghyun Choi, Sejie Takaki
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Patent number: 11812617Abstract: A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction.Type: GrantFiled: March 28, 2021Date of Patent: November 7, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sejie Takaki
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Patent number: 11805654Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.Type: GrantFiled: March 19, 2021Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO, LTD.Inventors: Sejie Takaki, JoonHee Lee
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Patent number: 11716854Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.Type: GrantFiled: September 17, 2020Date of Patent: August 1, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jiyoung Kim, Woosung Yang, Sejie Takaki
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Publication number: 20220139946Abstract: A semiconductor device includes a memory stack on a substrate, the memory stack including gate electrodes, insulating layers and mold layers, the mold layers being disposed at the same levels as the gate electrodes in a through electrode area, a channel structure extending vertically through the gate electrodes in a cell array area, and a dam structure disposed between the isolation insulating layers and surrounding the through electrode area in a top view. The dam structure includes a dam insulating layer having a dam shape, an inner insulating layer inside the dam insulating layer, and an outer insulating layer outside the dam insulating layer. The inner insulating layer includes first protrusions protruding in a horizontal direction, and the outer insulating layer includes second protrusions protruding in the horizontal direction.Type: ApplicationFiled: March 28, 2021Publication date: May 5, 2022Inventor: Sejie TAKAKI
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Publication number: 20210408027Abstract: A semiconductor device includes a peripheral circuit region with a first substrate, circuit devices on the first substrate, and a first wiring structure, a memory cell region with a second substrate that has a first region and a second region, gate electrodes stacked in the first region, channel structures that penetrate the gate electrodes, a first horizontal conductive layer on the second substrate in the first region, an insulating region on the second substrate in the second region, a second horizontal conductive layer on the first horizontal conductive layer and the insulating region, and a second wiring structure, and a third wiring structure that connects the first substrate to the second substrate, and includes an upper via that penetrates the second horizontal conductive layer, the insulating region, and the second substrate, and a lower wiring structure connected to the upper.Type: ApplicationFiled: March 19, 2021Publication date: December 30, 2021Inventors: SEJIE TAKAKI, JOONHEE LEE
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Publication number: 20210375920Abstract: A semiconductor device includes a pattern structure; a stack structure including gate and interlayer insulating layers on the pattern structure; and vertical structures penetrating through the stack structure, contacting the pattern structure. The pattern structure includes a lower pattern layer, an intermediate pattern layer, and an upper pattern layer sequentially stacked, the vertical structures including a vertical memory structure penetrating through the upper pattern and intermediate pattern layers and extending into the lower pattern layer, the intermediate pattern layer including a first portion, a second portion extending from the first portion and having a decreased thickness, and a third portion extending from the first portion, having an increased thickness, and contacting the vertical memory structure.Type: ApplicationFiled: February 16, 2021Publication date: December 2, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Yujin Seo, Euntaek Jung, Byoungil Lee, Seul Lee, Joonhee Lee, Changdae Jung, Bonghyun Choi, Sejie Takaki
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Publication number: 20210225869Abstract: A memory device includes a substrate, a stacked structure, channel layers, and separation layers. The substrate includes a first layer, a second layer on the first layer, and a third layer on the second layer/ The stacked structure including electrode layers stacked on the substrate. The channel layers extend in a direction perpendicular to an upper surface of the substrate, to penetrate through the stacked structure and to contact with the second layer in a direction horizontal to the upper surface of the substrate. The separation layers divide the stacked structure into unit structures. A first boundary between the first layer and the second layer below one or more of the separation layers is disposed to be lower than a second boundary between the first layer and the second layer that is located between an adjacent two channel layers.Type: ApplicationFiled: September 15, 2020Publication date: July 22, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Sejie Takaki
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Publication number: 20210217765Abstract: A 3D semiconductor memory device includes a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, an electrode structure on the second substrate, the electrode structure comprising stacked electrodes, and a vertical channel structure penetrating the electrode structure. The peripheral circuit structure includes a dummy interconnection structure under the second substrate. The dummy interconnection structure includes stacked interconnection lines, and a via connecting a top surface of an uppermost one of the interconnection lines to a bottom surface of the second substrate.Type: ApplicationFiled: September 17, 2020Publication date: July 15, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Jiyoung KIM, Woosung YANG, Sejie TAKAKI