Abstract: A method, apparatus, and electronic device for improving memory performance are disclosed. The method may include automatically checking reconfigurable logic for available memory and executing a first memory allocation to the available memory.

Abstract: Memory addresses for a data stream are generated by a stream parameter generator that calculates a set of stream parameters for each of a number of memory access patterns and a regional address generator that calculates a sequence of addresses of a memory access pattern from a corresponding set of stream parameters. The stream parameters, which may include START_ADDRESS, STRIDE, SKIP and SPAN values for example, are updated in accordance with an update( ) function. The update( ) function, which may be defined by a user, defines how stream parameters change from one memory access pattern to the next. In one application, the update( ) function describes how the position, shape and/or size of a region of interest in an image changes or is expected to change.

Abstract: A method and system for automatic configuration of processor hardware from an application program that has stream descriptor definitions, descriptive of memory access locations, data access thread definitions having a stream descriptor and a data channel source or sink as parameters, and computation thread definitions having a function pointer, a data channel source and a data channel sink as parameters. The application program is compiled to produce a description of the data flow between the threads as specified in the application program. The hardware is configured to have streaming memory interface devices operable to access a memory in accordance with the stream descriptor definitions, data path devices operable to process data in accordance with the computation thread definitions and data channels operable to connect the data path devices and streaming memory interface devices in accordance with the description of the data flow.

Abstract: Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Abstract: A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a computation specified by a streaming data flow graph. The candidate streaming processor circuit is evaluated with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output if the candidate streaming processor circuit satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate streaming processor circuits.

Abstract: In one embodiment, a subset of a set of streaming kernels of an application is selected for implementation on a reconfigurable processor. The streaming kernels are selected by first forming a stream flow graph of the application by parsing a program of instructions of the application, the stream flow graph having kernel nodes and edges, and determining benefit and cost values for each kernel node in the stream flow graph. Next, a subset of the kernel nodes that maximizes a weighted sum of the benefits values is selected, subject to a constraint that the sum of cost values is not greater than a prescribed value for the reconfigurable processor.