Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

Abstract: A semiconductor device includes a substrate including a first area and a second area, and first and second transistors formed in the first area and the second area, respectively. The first transistor includes a first gate insulating layer on the substrate, a first TiN layer on the first gate insulating layer contacting the first gate insulating layer, and a first filling layer on the first TiN layer. The second transistor includes a second gate insulating layer on the substrate, a second TiN layer on the second gate insulating layer contacting the second gate insulating layer, and a second filling layer on the second TiN layer. A threshold voltage of the first transistor is less than that of the second transistor, the second gate insulating layer does not comprise lanthanum, and an oxygen content of a portion of the first TiN layer is greater than that of the second TiN layer.

Abstract: A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.

Abstract: A semiconductor device includes a substrate having first and second regions, a first gate electrode layer on the first region, and including a first conductive layer, and a second gate electrode layer on the second region, and including the first conductive layer, a second conductive layer on the first conductive layer, and a barrier metal layer on the second conductive layer, wherein an upper surface of the first gate electrode layer is at a lower level than an upper surface of the second gate electrode layer.

Abstract: A semiconductor device includes a substrate including a first area and a second area, and first and second transistors formed in the first area and the second area, respectively. The first transistor includes a first gate insulating layer on the substrate, a first TiN layer on the first gate insulating layer contacting the first gate insulating layer, and a first filling layer on the first TiN layer. The second transistor includes a second gate insulating layer on the substrate, a second TiN layer on the second gate insulating layer contacting the second gate insulating layer, and a second filling layer on the second TiN layer. A threshold voltage of the first transistor is less than that of the second transistor, the second gate insulating layer does not comprise lanthanum, and an oxygen content of a portion of the first TiN layer is greater than that of the second TiN layer.

Abstract: A semiconductor device includes a substrate with first and second areas, a first trench in the first area, and first and second PMOS transistors in the first area and the second area, respectively. The first transistor includes a first gate insulating layer, a first TiN layer on and contacting the first gate insulating layer, and a first gate electrode on and contacting the first TiN layer. The second transistor includes a second gate insulating layer, a second TiN layer on and contacting the second gate insulating layer, and a first TiAlC layer on and contacting the second TiN layer. The first gate insulating layer, the first TiN layer, and the first gate electrode are within the first trench. The first gate electrode does not include aluminum. A threshold voltage of the first transistor is smaller than a threshold voltage of the second transistor.

Abstract: A semiconductor device includes a substrate having first and second active regions with a field insulating layer therebetween that contacts the first and second active regions, and a gate electrode on the substrate and traversing the first active region, the second active region, and the field insulating layer. The gate electrode includes a first portion over the first active region, a second portion over the second active region, and a third portion in contact with the first and second portions. The gate electrode includes an upper gate electrode having first through third thicknesses in the first through third portions, respectively, where the third thickness is greater than the first thickness, and smaller than the second thickness.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.

Abstract: A semiconductor device including a first fin pattern and a second fin pattern, which are in parallel in a lengthwise direction; a first trench between the first fin pattern and the second fin pattern; a field insulating film partially filling the first trench, an upper surface of the field insulating film being lower than an upper surface of the first fin pattern and an upper surface of the second fin pattern; a spacer spaced apart from the first fin pattern and the second fin pattern, the spacer being on the field insulating film and defining a second trench, the second trench including an upper portion and an lower portion; an insulating line pattern on a sidewall of the lower portion of the second trench; and a conductive pattern filling an upper portion of the second trench and being on the insulating line pattern.