Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.

Abstract: In an embodiment, a method of reducing resistance-capacitance delay along photodiode transfer lines of an image sensor includes forking a plurality of photodiode transfer lines each into a plurality of sublines coupled together and to a first decoder-driver at a first end of each subline; and distributing selection transistors of a plurality of multiple-photodiode cells among the plurality of sublines. In embodiments, the sublines may be recombined at a second end of the sublines and driven by a second decoder-driver at the second end.

Abstract: An image sensor includes an array of multiple-photodiode cells, each photodiode coupled through a selection transistor to a floating diffusion of the cell, the selection transistors controlled by respective transfer lines, a reset, a sense source follower, and a read transistor coupled from the source follower to a data line. The array includes phase detection rows with phase detection cells and normal cells; and a compensation row of more cells. In embodiments, each phase detection row has cells with at least one photodiode coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the row. In embodiments, the compensation row has cells with photodiodes coupled to the floating diffusion by selection transistors controlled by a transfer line separate from transfer lines of selection transistors of adjacent normal cells of the compensation row.

Abstract: An imaging device includes a pixel array of 1×3 pixel circuits that include 3 photodiodes in a column. Bitlines are coupled to the 1×3 pixel circuits. The bitlines are divided into groupings of 3 bitlines per column of the 1×3 pixel circuits. Each column of the 1×3 pixel circuits includes a plurality of first banks coupled to a first bitline, a plurality of second banks coupled to a second bitline, and a plurality of third banks coupled to a third bitline of a respective grouping of the 3 bitlines. The 1×3 pixel circuits are arranged into groupings of 3 1×3 pixel circuits per nine cell pixel structures that form a plurality of 3×3 pixel structures of the pixel array.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A pixel circuit, a method for performing a pixel-level background light subtraction, and an imaging device are disclosed. In one example of the present disclosure, the pixel circuit includes an overflow gate transistor, a photodiode, and two taps. Each tap of the two taps is configured to store a background signal that is integrated by the photodiode, subtract the background signal from a floating diffusion, store a combined signal that is integrated by the photodiode at the floating diffusion, and generate a demodulated signal based on a subtraction of the background signal from the floating diffusion and a storage of the combined signal that is integrated at the floating diffusion.

Abstract: A house number light includes a frame defining an opening in a central portion and having a side opening along an inside face. The frame includes light sources, first and second power sources configured to provide electric power to the light sources, and a control circuit connected between the first power source and the light sources and connected between the second power source and the light sources. The control circuit electrically couples one of the first and the second power sources to the light sources at a time. If the first power source is electrically coupled to the light sources, electrical energy from the first power source passes through the control circuit to the light sources, and if the second power source is electrically coupled to the light sources, electrical energy provided by the second power source passes through the control circuit to the light sources.

Abstract: A system controls a switching power converter to power LED strings using a predictive feedforward control mechanism. An LED controller determines programmed current levels and duty cycles for driving LED strings. The LED controller determines a predicted load for a subsequent cycle of a switching power converter driving the LED strings based on the programmed current levels and duty cycles. A power conversion controller uses the predicted load information to control switching of the switching power converter. This improves the dynamic response of the switching converter to changing load conditions, thereby improving overall power efficiency and performance of the system.

Abstract: A system controls a switching power converter to power LED strings using a predictive feedforward control mechanism. An LED controller determines programmed current levels and duty cycles for driving LED strings. The LED controller determines a predicted load for a subsequent cycle of a switching power converter driving the LED strings based on the programmed current levels and duty cycles. A power conversion controller uses the predicted load information to control switching of the switching power converter. This improves the dynamic response of the switching converter to changing load conditions, thereby improving overall power efficiency and performance of the system.

Abstract: A digital phase lock loop circuit provides an output with reduced jitter. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: A digital phase lock loop circuit with reduced jitter at the output is disclosed. The digital phase lock loop circuit includes a phase frequency detector that determines a phase difference between a feedback signal and a reference frequency signal to generate an error signal indicative of the phase difference. A numerically controlled oscillator generates a first oscillator output signal with a frequency proportional to the error signal and a second oscillator output signal indicative of jitter of the first oscillator output signal in reference to the reference frequency signal. A phase accuracy extender determines a delay amount from the second oscillator output signal and delays the first oscillator output signal by the delay amount to generate a phase-enhanced output signal with edges aligned with one of a plurality of reference clock signals.

Abstract: The mixer circuit is a singled ended input to a double balanced high dynamic range mixer with only two base-emitter junctions across the supply. It provides for the use of bondwires to off chip ground as DC block and DC feed elements. The single ended input and differential output balanced mixer is well suited for the input stage of an integrated radio receiver—off chip circuitry is usually single ended, but on chip circuits are usually differential. No off chip differential RF circuits or baluns are required which reduces off chip component count and improves radio performance. The mixer circuit has lower LO drive requirements because of the DC coupled LO port. This results in better radio performance and a smaller die area because of the DC coupled IF port.