Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.

Abstract: Memory storage requirements for digital signal processing operations, for example, motion-compensated video scan rate conversion, that produce intermediate output data, which is then used as an input to the operation, are reduced by reordering operations and organizing memory allocations in a special manner to allow intermediate output at a particular execution time, to substantially share the same memory space as the intermediate output of a previous execution time. Such a reduction in the amount of memory required for processing operations advantageously reduces cost and power consumption.

Abstract: According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2×2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2×2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: For compensation and/or estimation of motion in a digital video image a search area or window (S) is defined for an actual image segment (BD-B) such that all data that can be accessed via motion vectors from all pixels in the actual image segment (BD-B) is contained in the search area (S).

Abstract: According to an example embodiment, the present invention is directed to pixel-data processing that includes scanning a first 2×2 line in each of a series of immediately adjacent pixel blocks, prior to scanning a second 2×2 line in each of the series of pixel blocks. Each scanned line is then processed for motion compensation in a manner that addresses challenges, including those discussed above, related to buffer size requirements, power consumption requirements and latency.

Abstract: A pixel-data processing circuit adapted to resize pixel data in a first vertically processing mode is reconfigurable to operate in a nonresizing mode, wherein each mode receives pixel data at a first pixel rate and outputs pixel data at a different pixel rate. In one particular example embodiment, pixels are received at two pixels per cycle and output to a storage unit at one pixel per cycle. In a first operational resizing mode, the embodiment includes vertically processing pixel data including polyphase filtering and line-buffering the pixel data, resizing the received pixel data by circulating the data in the line buffers and by filtering the circulated data for the polyphase filtering, and presenting resized pixel data for storage at the first pixel rate. In a second operational nonresizing mode, the pixel data is processed by double-line buffering the pixel data, bypassing the polyphase filtering, and presenting nonresized pixel data for storage at the rate of one pixel per cycle.

Abstract: A VLIW processor has first and second functional units for executing first and second commands in a first instruction word. The first and second commands comprise a first field and a second field, respectively, in ordered concatenations of fields. The processor has a third functional unit for executing a third command in a second instruction word. The third command comprises both the first and second fields.

Abstract: A novel method is taught to quickly and easily produce assember code from a single embedded file which can include high level language code written in any of a number of high level languages interspersed, if desired, among assembler code itself.