Abstract: A method includes receiving a physical circuit design file that includes physical circuit partitions that are each mapped to a respective chip. The physical circuit partitions are connected to one another by a respective timing path having an original delay. The method further includes determining a slack budget of the respective timing path, and determining a delay upper bound value based on a shortest timing path delay and the slack budget. Further, the method includes updating the delay upper bound of the respective timing path based on the slack budget, assigning an interconnection delay upper bound to a physical interconnection between at least two chips based on the updated slack budget of the respective timing path, determining a multiplexing data ratio (XDR) based on at least the interconnection delay upper bound of the physical interconnection, and performing routing between the at least two chips based on the XDR.