Patents by Inventor Selvarajan Murugan

Selvarajan Murugan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8043545
    Abstract: Methods and apparatus to evenly clamp semiconductor substrates in a transfer mold process are disclosed. A disclosed split mold base includes a first plate having a first surface, a second plate having a second surface opposite the first surface, and a plurality of springs that are disposed between the first and second plates to distribute a clamping pressure applied by a mold press.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: October 25, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Selvarajan Murugan, Abdul Rahman Mohamed Rafaie
  • Publication number: 20090166923
    Abstract: Methods and apparatus to evenly clamp semiconductor substrates in a transfer mold process are disclosed. A disclosed split mold base includes a first plate having a first surface, a second plate having a second surface opposite the first surface, and a plurality of springs that are disposed between the first and second plates to distribute a clamping pressure applied by a mold press.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Inventors: Selvarajan Murugan, Abdul Rahman Mohamed Rafaie
  • Publication number: 20070087079
    Abstract: According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool includes a first mold plate that includes a first non-planar surface and a second mold plate that includes a second non-planar surface. The first and second non-planar surfaces form upper and lower surfaces of a mold cavity when the first and second mold plates are engaged. The mold tool also includes a distribution system coupled to the mold cavity. The distribution system transfers a mold compound into the mold cavity to substantially encapsulate an integrated circuit. The distribution system includes a gate runner coupled to the mold cavity. The gate runner funnels the mold compound into the mold cavity. The distribution system also includes a bridge insert that decreases wear on the gate runner as the mold compound is transferred through the gate runner.
    Type: Application
    Filed: December 20, 2006
    Publication date: April 19, 2007
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Selvarajan Murugan
  • Patent number: 7169345
    Abstract: According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool includes a first mold plate that includes a first non-planar surface and a second mold plate that includes a second non-planar surface. The first and second non-planar surfaces form upper and lower surfaces of a mold cavity when the first and second mold plates are engaged. The mold tool also includes a distribution system coupled to the mold cavity. The distribution system transfers a mold compound into the mold cavity to substantially encapsulate an integrated circuit. The distribution system includes a gate runner coupled to the mold cavity. The gate runner funnels the mold compound into the mold cavity. The distribution system also includes a bridge insert that decreases wear on the gate runner as the mold compound is transferred through the gate runner.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: January 30, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Selvarajan Murugan
  • Patent number: 7005101
    Abstract: The mold for a thin package uses a gate which has a high aspect ratio, about 30 degrees or greater throughout the length of the gate. Additionally, the depth of the gate goes to zero at a point outside of the area of the finished package, but within the dam bars, so that the leadframe space acts as a virtual gate. This reduces the need for trimming and lowers stress on the finished package.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: February 28, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Selvarajan Murugan
  • Publication number: 20050046079
    Abstract: According to one embodiment of the invention, a system for packaging integrated circuits includes a mold tool for packaging integrated circuits. The mold tool includes a first mold plate that includes a first non-planar surface and a second mold plate that includes a second non-planar surface. The first and second non-planar surfaces form upper and lower surfaces of a mold cavity when the first and second mold plates are engaged. The mold tool also includes a distribution system coupled to the mold cavity. The distribution system transfers a mold compound into the mold cavity to substantially encapsulate an integrated circuit. The distribution system includes a gate runner coupled to the mold cavity. The gate runner funnels the mold compound into the mold cavity. The distribution system also includes a bridge insert that decreases wear on the gate runner as the mold compound is transferred through the gate runner.
    Type: Application
    Filed: August 27, 2003
    Publication date: March 3, 2005
    Inventor: Selvarajan Murugan
  • Publication number: 20030132019
    Abstract: The mold for a thin package uses a gate which has a high aspect ratio, e.g. about 30 degrees or greater throughout the length of the gate. Additionally, the depth of the gate goes to zero at a point outside of the area of the finished package, but within the dam bars, so that the leadframe space acts as a virtual gate. This reduces the need for trimming and lowers stress on the finished package.
    Type: Application
    Filed: March 3, 2003
    Publication date: July 17, 2003
    Applicant: Texas Instruments Incorporated
    Inventor: Selvarajan Murugan
  • Publication number: 20020043389
    Abstract: The mold for a thin package uses a gate which has a high aspect ratio, e.g. about 30 degrees or greater throughout the length of the gate. Additionally, the depth of the gate goes to zero at a point outside of the area of the finished package, but within the dam bars, so that the leadframe space acts as a virtual gate. This reduces the need for trimming and lowers stress on the finished package.
    Type: Application
    Filed: September 13, 2001
    Publication date: April 18, 2002
    Inventor: Selvarajan Murugan