Patents by Inventor Semeon Altshuler

Semeon Altshuler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of high aspect ratio plug fill
    Patent number: 8236691
    Abstract: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Yakov Shor, Semeon Altshuler, Maor Rotlain, Yigal Alon, Dror Horvitz
  • Forming low dielectric constant dielectric materials
    Patent number: 7935627
    Abstract: In some embodiments, a damascene structure may be formed with metal lines separated by a dielectric layer. Portions of the dielectric layer may be ion implanted with carbon and/or inert species to lower selectively the dielectric constant, while leaving the bulk of the dielectric layer unaffected by the implant. As a result, suitably low dielectric constants can be achieved in damascene dielectric layers with sufficient mechanical strength.
    Type: Grant
    Filed: March 5, 2009
    Date of Patent: May 3, 2011
    Inventors: Yakov Shor, Semeon Altshuler, Valery Shumilin, Alexander Ripp
  • METHOD OF HIGH ASPECT RATIO PLUG FILL
    Publication number: 20100167532
    Abstract: A method of plug fill for high aspect ratio plugs wherein a nucleation layer is formed at a bottom of a via and not on the sidewalls. The plug fill is in the direction from bottom to top of the via and not inwards from the sidewalls. The resulting plug is voidless and seamless.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Inventors: Yakov Shor, Semeon Altshuler, Maor Rotlain, Yigal Alon, Dror Horvitz
  • Integrated circuit with embedded contacts
    Publication number: 20090302477
    Abstract: In some embodiments, disclosed is an interconnect structure with embedded plugs.
    Type: Application
    Filed: June 6, 2008
    Publication date: December 10, 2009
    Inventors: Yakov Shor, Yuval Najari, Lior Gadot, Effi Aboody, Semeon Altshuler, Nuriel Amir
  • Through-wafer vias and surface metallization for coupling thereto
    Patent number: 7510907
    Abstract: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.
    Type: Grant
    Filed: June 22, 2005
    Date of Patent: March 31, 2009
    Assignee: Intel Corporation
    Inventors: John Heck, Qing Ma, Quan Tran, Tsung-Kuan Allen Chou, Semeon Altshuler, Boaz Weinfeld
  • Through-wafer vias and surface metallization for coupling thereto
    Publication number: 20060289967
    Abstract: An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.
    Type: Application
    Filed: June 22, 2005
    Publication date: December 28, 2006
    Inventors: John Heck, Qing Ma, Quan Tran, Tsung-Kuan Chou, Semeon Altshuler, Boaz Weinfeld