Patents by Inventor SEMICONDUCTOR MANUFACTURING INTERNA

SEMICONDUCTOR MANUFACTURING INTERNA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130168747
    Abstract: The present invention discloses a method for manufacturing a semiconductor device. According to the method provided by the present disclosure, a dummy gate is formed on a substrate, removing the dummy gate to form an opening having side walls and a bottom gate, a dielectric material is formed on at least a portion of the sidewalls of the opening and the bottom surface of the opening, and a pre-treatment is performed to a portion of the dielectric material layer on the sidewalls of the opening, and thus the properties of the dielectric material is changed, and then the pre-treated dielectric material on the sidewalls of the opening is removed by a selective process. The semiconductor device manufactured by using the method of the present disclosure is capable of effectively reducing parasitic capacitance.
    Type: Application
    Filed: September 20, 2012
    Publication date: July 4, 2013
    Applicant: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION
    Inventors: SEMICONDUCTOR MANUFACTURING INTERNA, SEMICONDUCTOR MANUFATURING INTERNATI
  • Publication number: 20130119496
    Abstract: The present disclosure describes a semiconductor MRAM device and a manufacturing method. The device reduces magnetic field induction “interference” (disturbance) phenomenon between adjacent magnetic tunnel junctions when data is written and read. This semiconductor MRAM device comprises a magnetic tunnel junction unit and a magnetic shielding material layer covering the sidewalls of the magnetic tunnel junction unit. The method for manufacturing a semiconductor device comprises: forming a magnetic tunnel junction unit, depositing an isolation dielectric layer to cover the top and the sidewall of the magnetic tunnel junction unit, and depositing a magnetic shielding material layer on the isolation dielectric layer.
    Type: Application
    Filed: October 17, 2012
    Publication date: May 16, 2013
    Applicants: SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (BEIJING), SEMICONDUCTOR MANUFACTURING INTERNATIONAL CORPORATION (SHANGHAI)
    Inventors: SEMICONDUCTOR MANUFACTURING INTERNA, SEMICONDUCTOR MANUFACTURING INTERNA