Patents by Inventor Sen-Bor Jan

Sen-Bor Jan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11342297
    Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sen-Bor Jan, Sung-Feng Yeh
  • Patent number: 11335656
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: May 17, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11309243
    Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: April 19, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Publication number: 20220012402
    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang
  • Publication number: 20210384147
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.
    Type: Application
    Filed: August 19, 2021
    Publication date: December 9, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan, Chih-Chia Hu
  • Publication number: 20210327789
    Abstract: A manufacturing method of a semiconductor structure includes at least the following steps. Forming a first tier includes forming a conductive via extending from a lower portion of a first interconnect structure into a first semiconductor substrate underlying the lower portion; forming an upper portion of the first interconnect structure on the conductive via and the lower portion; forming a first surface dielectric layer on the upper portion; and forming a first and a second bonding connectors in the first surface dielectric layer. The first bonding connector extends to be in contact with an upper-level interconnecting layer of the first interconnect structure, the second bonding connector is narrower than the first bonding connector and extends to be in contact with a lower-level interconnecting layer of the first interconnect structure, and a top surface of the conductive via is between the upper-level interconnecting layer and the first semiconductor substrate.
    Type: Application
    Filed: July 2, 2021
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 11107779
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan, Chih-Chia Hu
  • Patent number: 11094613
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 11080455
    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang
  • Publication number: 20210175154
    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
    Type: Application
    Filed: February 22, 2021
    Publication date: June 10, 2021
    Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20210173998
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Application
    Filed: February 19, 2021
    Publication date: June 10, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan CHANG, Chin-Chou LIU, Chin-Her CHIEN, Cheng-Hung YEH, Po-Hsiang HUANG, Sen-Bor JAN, Yi-Kan CHENG, Hsiu-Chuan SHU
  • Publication number: 20210118827
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first spiral section and first bonding metallurgies of an inductor. The first bonding metallurgies are connected to the first spiral section. The second die is bonded to the first die. The second die includes a second spiral section and second bonding metallurgies of the inductor. The second bonding metallurgies are connected to the second spiral section. The inductor extends from the first die to the second die.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 22, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan, Chih-Chia Hu
  • Publication number: 20210098409
    Abstract: A package structure including at least one die laterally encapsulate by an encapsulant, a bonding film and an interconnect structure is provided. The bonding film is located on a first side of the encapsulant, and the bonding film includes a first alignment mark structure. The package structure further includes a semiconductor material block located on the bonding film. The interconnect structure is located on a second side of the encapsulant opposite to the first side, and the interconnect structure includes a second alignment mark structure. A location of the first alignment mark structure vertically aligns with a location of the second alignment mark structure.
    Type: Application
    Filed: May 19, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen, Jie Chen, Sen-Bor Jan, Sung-Feng Yeh
  • Publication number: 20210082816
    Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.
    Type: Application
    Filed: September 17, 2019
    Publication date: March 18, 2021
    Inventors: Fong-yuan Chang, Noor Mohamed Ettuveettil, Po-Hsiang Huang, Sen-Bor Jan, Ming-Fa Chen, Chin-Chou Liu, Yi-Kan Cheng
  • Patent number: 10949597
    Abstract: The present disclosure describes structures and methods for a via structure for three-dimensional integrated circuit (IC) packaging. The via structure includes a middle portion that extends through a planar structure and a first end and a second end each connected to the middle portion and on a different side of the planar structure. One or more of the first end and the second end includes one or more of a plurality of vias and a pseudo metal layer.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chin-Chou Liu, Chin-Her Chien, Cheng-Hung Yeh, Po-Hsiang Huang, Sen-Bor Jan, Yi-Kan Cheng, Hsiu-Chuan Shu
  • Publication number: 20210066192
    Abstract: A package has a first region and a second region. The package includes a first die, a second die, an encapsulant, and an inductor. The second die is stacked on and bonded to the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. A metal density in the first region is greater than a metal density in the second region.
    Type: Application
    Filed: July 15, 2020
    Publication date: March 4, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Sen-Bor Jan
  • Publication number: 20210057309
    Abstract: A semiconductor structure and the manufacturing method thereof are provided. A semiconductor structure includes a semiconductor substrate, a plurality of interconnecting layers, a first connector, and a second connector. The semiconductor substrate includes a plurality of semiconductor devices therein. The interconnecting layers are disposed over the semiconductor substrate and electrically coupled to the semiconductor devices. The first connector is disposed over the plurality of interconnecting layers and extends to be in contact with a first level of the plurality of interconnecting layers. The second connector is disposed over the plurality of interconnecting layers and substantially leveled with the first connector.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chia Hu, Hsien-Wei Chen, Ming-Fa Chen, Sen-Bor Jan
  • Patent number: 10930580
    Abstract: A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: February 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Sen-Bor Jan, Hsien-Wei Chen, Ming-Fa Chen
  • Publication number: 20210005561
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Publication number: 20200373253
    Abstract: A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Inventors: Chih-Chia Hu, Chun-Chiang Kuo, Sen-Bor Jan, Ming-Fa Chen, Hsien-Wei Chen