Abstract: A method for passivating a target layer. There is first provided a substrate. There is then formed over the substrate a target layer, where the target layer is susceptible to corrosion incident to contact with a corrosive material employed for further processing of the substrate. There is then treated, while employing a first plasma method employing a first plasma gas composition comprising an oxidizing gas, the target layer to form an oxidized target layer having an inhibited susceptibility to corrosion incident to contact with the corrosive material employed for further processing of the substrate. Finally, there is then processed further, while employing the corrosive material, the substrate. The method is useful when forming bond pads within microelectronic fabrications.

Abstract: A device with a plurality of structures with different resistance values is formed on a substrate. A polysilicon layer is formed upon the substrate. A silicon oxide layer is formed over the substrate. A hard masking layer is formed over the silicon oxide layer. The hard masking layer includes a full thickness portion and a thinner portion. The polysilicon layer below the full thickness portion is lightly doped forming a high resistance region. Below the thinner portion the polysilicon layer is heavily doped forming a low resistance region. However, in spite of the differences in resistance, the high resistance region and the low resistance region have the same thickness.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A new method for improving particle level, stability of etch rate, and better etch uniformity by using a dry plasma clean to remove polymer buildup from the upper electrode and walls of an etch chamber after spin-on-glass etchback is described. An etching chamber having a lower electrode, upper electrode, and interior walls is provided. Spin-on-glass etchback is performed within the etching chamber whereby a polymer buildup forms on surfaces of chamber. A dummy wafer is placed into the etching chamber and the polymer buildup within the chamber is removed using a dry plasma cleaning process.

Abstract: A method is disclosed to form a reliable silicon nitride spacer between the lower edges of the floating gate and the control gate of a split-gate flash memory cell. This is accomplished by forming a floating gate with vertical sidewalls, forming a high temperature oxide layer followed by silicon nitride layer over the floating gate including the vertical sidewalls, ion implanting the nitride layer and then selectively etching it to form a robust silicon nitride spacer of well defined rectangular shape.

Abstract: A protective tape is applied to the device side of a wafer (to protect it during an operation to grind the back side of the wafer) after the surface has been prepared to present only sloping surfaces to the tape. This profile prevents the otherwise sharp edges of the holes for the bonding pads from cutting into the adhesive of the tape and causing adhesive particles to remain on the wafer surface after the tape has been removed. Particles of resist can interfere with attaching wires to the bonding pads. The tape receiving surface of the wafer is commonly formed by a passivation layer and by bonding pad sites that are exposed through holes in the passivation layer. These sloping profiles can be formed by giving a sloping profile to the holes in the photoresist before the holes are etched. Alternatively the holes can be etched suitably wider at the top than at the bottom.

Abstract: A method to prevent threshold shifts in MOS transistors due to auto-doping from heavily doped polysilicon layers. Isolation regions are provided in a semiconductor substrate separating active areas. A gate oxide layer is formed over the surface of the semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A tungsten silicide layer is deposited overlying the polysilicon layer. The tungsten silicide layer and the first polysilicon layer are etched to form MOS gates and bottom electrodes for dual polysilicon capacitors. An interpoly dielectric layer is deposited overlying entire surface of the semiconductor substrate. A doped polysilicon layer is deposited overlying the interpoly dielectric layer. A sealing oxide layer is deposited overlying the doped polysilicon layer to prevent out-diffusion of impurity ions into the semiconductor substrate and thereby preventing auto-doping. The tungsten silicide layer is annealed. Ions are implanted to form drain and source regions.

Abstract: A new method of forming polysilicon resistors having differing resistances using a dual polysilicon process is described. A first polysilicon layer is deposited over a dielectric layer on a semiconductor substrate. The first polysilicon layer is etched away where it is not covered by a mask. Thereafter, a second polysilicon layer is deposited overlying the first polysilicon layer and the dielectric layer. The first and second polysilicon layers are patterned to form a first polysilicon structure comprising the first and second polysilicon layers over the dielectric layer and a second polysilicon structure comprising the second polysilicon layer overlying the dielectric layer. The first and second polysilicon structures are doped to form the first polysilicon structure having a first resistance and the second polysilicon structure having a second resistance wherein the first resistance is lower than the second resistance.

Abstract: A method is provided for forming a plurality of structures with different resistance values in a single polysilicon film as follows. Form a polysilicon layer upon a substrate. Pattern the polysilicon to expose a portion thereof which is to be reduced in thickness. Partially etch through the polysilicon to produce a reduced thickness thereof while leaving the remainder of the polysilicon with the original thickness. Dope the polysilicon layer through the polysilicon with variable doping as a function of the reduced thickness and the original thickness of the polysilicon.

Abstract: This method forms structures with different resistance values from a single polysilicon film formed on a substrate. Form a hard masking layer on the polysilicon film. Form a photoresist mask over the hard masking layer. Partially etch the hard masking layer through the photoresist mask to reduce the thickness of the polysilicon while leaving the remainder of the hard masking layer with the original thickness. The thickness is reduced in locations where a low resistance is to be located in the polysilicon film. Then dope the polysilicon layer through the hard masking layer with variable doping as a function of the reduced thickness and the original thickness of the hard masking layer.

Abstract: A method for forming n- and p-type contacts for CMOS integrated circuits is described wherein the contact openings are ion implanted after being etched to provide supplemental doping to the exposed device elements in order to secure a reliable low resistance interface with subsequently deposited contact metallurgy The p-type contact openings and the n-type contact openings are patterned, etched, and ion implanted separately, thereby requiring only two photolithographic steps. By etching and implanting the p-contacts and n-contacts separately, the method eliminates one highly complex and contaminative photolithographic step and introduces a less complex etch step with reduced contamination risk, thereby achieving a cost saving by improving yield and reducing process time. It is optional which contacts are processed first.

Abstract: A new method of removing impurities and moisture from the surface of a wafer and thereby preventing polysilicon residue is described. A dielectric layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the dielectric layer. A hard mask layer is deposited overlying the polysilicon layer and patterned to form a hard mask. The wafer is cleaned whereby moisture and impurities form on the surfaces of the hard mask and the polysilicon layer. Thereafter, the wafer is heat treated whereby the moisture and impurities are removed. Thereafter, the polysilicon layer is etched away where it is not covered by the hard mask to complete formation of a polysilicon line on a wafer in the fabrication of an integrated circuit.

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract: A method for etching bonding pad access openings in a passivation layer of an integrated circuit is described. The method utilizes a two step etching procedure wherein the first step etches isotropically through a major portion of the passivation layer under conditions which provide very high etch rate selectivities of the passivation material to the photoresist. These high selectivitities result in virtually no erosion of the photoresist while the greater part of the opening is etched. A second anisotropic etch step wherein the base of the access opening is defined faithfully replicates the dimensions of the mask pattern. This two step etch process permits the use of photoresist layers of moderate thickness as well as photoresist layers with thin regions, such as occur when the photoresist is deposited over the uneven surface topography typically found on unplanarized passivation layers.

Abstract: The polymeric residues which remain after the plasma-enhanced subtractive etching of polycrystalline layers in reactive halogen-containing gases are removed by a combination ashing in oxygen gas and subsequent removal with an organic solvent.

Abstract: A process for creating field oxide isolation for the micron and sub-micron devices in the high density integrated circuits has been developed. The junction leakage problem resulted from the trenches in the substrate formed after the removal of the silicon nitride mask, is avoided. The encroachment of the "bird's beak" into the small active device region is also minimized by this invention. These goals are accomplished by the addition of a polysilicon or amorphous silicon refill layer in the trenches after the removal of the silicon nitride oxidation mask in the isolation region, prior to field oxide oxidation process.

Abstract: A protective cap of dielectric material is deposited by plasma-enhanced chemical vapor deposition on the surface of electrical bonding pads of semiconductor integrated circuits prior to deposition of the final passivation layer. The protective cap serves to isolate the pad surface from electrochemical or other interaction with the etching solution used to open contact holes through the passivation layer. This prevents the formation of surface damage and residues on the pad which lead to yield and reliability problem with integrated circuits.

Abstract: A patterned silicon nitride layer formed over a semiconductor integrated circuit wafer having a layer of pad oxide is often used as a mask for subsequent processing steps. Etching of the silicon nitride layer is difficult to control and can create defects in the pad oxide layer which are difficult to detect before the manufacture of the semiconductor integrated circuit wafer is completed. A method is described using potassium hydroxide treatment and scanning electron microscope evaluation of a test wafer for detection of defects at the silicon nitride etching step. Continued processing of defective wafers can be terminated and the silicon nitride etching step can be controlled using this method.