Patents by Inventor Sen-Hong Syue

Sen-Hong Syue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006063
    Abstract: Embodiment methods for performing a high pressure anneal process during the formation of a semiconductor device, and embodiment devices therefor, are provided. The high pressure anneal process may be a dry high pressure anneal process in which a pressurized environment of the anneal includes one or more process gases. The high pressure anneal process may be a wet anneal process in which a pressurized environment of the anneal includes steam.
    Type: Application
    Filed: May 20, 2019
    Publication date: January 2, 2020
    Inventors: Szu-Ying Chen, Ya-Wen Chiu, Cheng-Po Chau, Y.C. Chan, C.P. Liao, Y.H. Wang, Sen-Hong Syue
  • Publication number: 20190139814
    Abstract: A semiconductor structure includes a semiconductor substrate, a first fin, a second fin, a first isolation structure, and a second isolation structure. The semiconductor substrate has a memory device region and a logic core region. The first fin is in the memory device region of the semiconductor substrate. The second fin is in the logic core region of the semiconductor substrate. The first isolation structure is around the first fin. The second isolation structure is around the second fin, and a thickness of the first isolation structure is different from a thickness of the second isolation structure.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta WU, Chii-Ming WU, Sen-Hong SYUE, Cheng-Po CHAU
  • Patent number: 10157770
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta Wu, Chii-Ming Wu, Sen-Hong Syue, Cheng-Po Chau
  • Publication number: 20180151414
    Abstract: A semiconductor device includes a substrate, a first isolation structure, a second isolation structure STI, and semiconductor fins. The first isolation structure is on the substrate and has a first thickness. The second isolation structure abuts the first isolation structure and has a second thickness. The first thickness is different from the second thickness. The semiconductor fins respectively abut the first isolation structure and the second isolation structure.
    Type: Application
    Filed: July 26, 2017
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Ta WU, Chii-Ming WU, Sen-Hong SYUE, Cheng-Po CHAU
  • Patent number: 9945048
    Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: April 17, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Hong Syue, Pu-Fang Chen, Shiang-Bau Wang
  • Patent number: 9929268
    Abstract: A method of fabricating a FinFET includes at last the following steps. A <551> direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the <551> direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chii-Ming Wu, Ru-Shang Hsiao, Hung Pin Chen, Sen-Hong Syue, Chi-Cherng Jeng
  • Publication number: 20170301793
    Abstract: A method of fabricating a FinFET includes at last the following steps. A <551> direction is determined by tilting 8.05±2 degrees from a normal vector of a (110) lattice plane of a semiconductor substrate. The semiconductor substrate is patterned along a lattice plane perpendicular to the <551> direction, so as to form a plurality of trenches in the semiconductor substrate and at least one semiconductor fin having sidewalls disposed on a (551) lattice plane. Insulators are in the trenches. A gate stack is formed over portions of the semiconductor fin and over portions of the insulators. Strained material portions are formed over the semiconductor fins revealed by the gate stack.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: Chii-Ming Wu, Ru-Shang Hsiao, Hung Pin Chen, Sen-Hong Syue, Chi-Cherng Jeng
  • Patent number: 9396986
    Abstract: Forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer involves performing an implant to generate passages in the upper portion of the flowable dielectric layer. The passages enable oxygen source in a thermal anneal to reach the flowable dielectric layer near the bottom of the STI structure during the thermal anneal to convert a SIONH network of the reflowable dielectric layer to a network of SiOH and SiO. The passages also help to provide escape paths for by-products produced during another thermal anneal to convert the network of SiOH and SiO to SiO2.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sen-Hong Syue, Ziwei Fang
  • Publication number: 20150099342
    Abstract: Forming a shallow trench isolation (STI) structure filled with a flowable dielectric layer involves performing an implant to generate passages in the upper portion of the flowable dielectric layer. The passages enable oxygen source in a thermal anneal to reach the flowable dielectric layer near the bottom of the STI structure during the thermal anneal to convert a SIONH network of the reflowable dielectric layer to a network of SiOH and SiO. The passages also help to provide escape paths for by-products produced during another thermal anneal to convert the network of SiOH and SiO to SiO2.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 9, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Hsiung Tsai, Sen-Hong Syue, Ziwei Fang
  • Patent number: 8932945
    Abstract: A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Hong Syue, Chung-Chun Ho, Pu-Fang Chen, Shiang-Bau Wang
  • Publication number: 20140011348
    Abstract: A system and method for mitigating annealing fingerprints in semiconductor wafers is provided. An embodiment comprises aligning the semiconductor wafers prior to each annealing step. This alignment generates similar or identical fingerprints in each of the semiconductor wafers manufactured. With the fingerprint known, a single compensation model for a subsequent photoresist may be utilized to compensate for the fingerprint in each of the semiconductor wafers.
    Type: Application
    Filed: July 9, 2012
    Publication date: January 9, 2014
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Hong Syue, Chung-Chun Ho, Pu-Fang Chen, Shiang-Bau Wang
  • Publication number: 20130337631
    Abstract: A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sen-Hong Syue, Pu-Fang Chen, Shiang-Bau Wang
  • Patent number: 7947551
    Abstract: An embodiment of the disclosure includes a method of forming a shallow trench isolation structure. A substrate is provided. The substrate includes a top surface. A trench is formed to extend from the top surface into the substrate. The trench has sidewalls and a bottom surface. A silicon liner layer is formed on the sidewalls and the bottom surface. A flowable dielectric material is filled in the trench. An anneal process is performed to densify the flowable dielectric material and convert the silicon liner layer into a silicon oxide layer simultaneously.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: May 24, 2011
    Inventors: Sen-Hong Syue, Bor Chiuan Hsieh, Shiang-Bau Wang