Patents by Inventor Sen-Nan Lee

Sen-Nan Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060048462
    Abstract: The present invention relates to an aseismatic support unit, and more particularly to an aseismatic support unit capable of being easily and fitly in-situ assembled to become an aseismatic system. The aseismatic support unit is mounted between a base and a loaded article, comprising a lower support member, an upper support member and a plurality of aseismatic units mounted therebetween. Each of the aseismatic units includes a lower carry member having an upward carry surface, an upper carry member having a downward carry surface and a support roller mounted therebetween. When an earthquake happens, shakes are transmitted from the base. Then, the aseismatic support unit of the present invention diminishes the extent of the shakes of the load article placed over the upper support member and thus prevent the loaded article from overturn and damage as a result of the earthquake.
    Type: Application
    Filed: July 22, 2005
    Publication date: March 9, 2006
    Applicants: VIO Creation Technology Inc., National Center for Research on Earthquake Engineering
    Inventors: Chih-Hung Huang, Sen-Nan Lee, Kuo-Chun Chang
  • Patent number: 6955467
    Abstract: A seismic isolation bearing assembly includes a frame unit including upper and lower frames and defining a plurality of upper and lower sub-frames, and a plurality of bearing units, each of which is mounted in a mounting cell defined by a respective one of the upper sub-frames and a respective one of the lower sub-frames, and each of which includes spaced apart upper and lower load plates and a bearing interposed between and in sliding contact with the upper and lower load plates. The upper load plate is secured to the respective one of the upper sub-frames. The lower load plate is secured to the respective one of the lower sub-frames.
    Type: Grant
    Filed: April 9, 2004
    Date of Patent: October 18, 2005
    Assignee: National Applied Research Laboratories
    Inventors: Kuo-Chun Chang, Jenn-Shin Hwang, George C. Lee, Sen-Nan Lee
  • Publication number: 20050100253
    Abstract: A seismic isolation bearing assembly includes a frame unit including upper and lower frames and defining a plurality of upper and lower sub-frames, and a plurality of bearing units, each of which is mounted in a mounting cell defined by a respective one of the upper sub-frames and a respective one of the lower sub-frames, and each of which includes spaced apart upper and lower load plates and a bearing interposed between and in sliding contact with the upper and lower load plates. The upper load plate is secured to the respective one of the upper sub-frames. The lower load plate is secured to the respective one of the lower sub-frames.
    Type: Application
    Filed: April 9, 2004
    Publication date: May 12, 2005
    Inventors: Kuo-Chun Chang, Jenn-Shin Hwang, George Lee, Sen-Nan Lee
  • Patent number: 6277751
    Abstract: A method for planarizing a semiconductor wafer. An insulation layer is formed over the wafer. A spin-on-glass layer is coated over the insulation layer. Subsequently, the spin-on-glass layer is baked to smooth out its upper surface. A chemical-mechanical polishing process is carried out to planarize the insulation layer. The method eliminates recess cavities in the more loosely packed device region of the insulation layer after a planarization process.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: August 21, 2001
    Assignee: Worldwide Semiconductor Manufacturing Corp.
    Inventors: Pao-Kang Niu, Chang-Sheng Lee, Bih-Tiao Lin, Sen-Nan Lee
  • Patent number: 6116991
    Abstract: A chemical-mechanical polishing station comprises a polishing table that has concentric rings. The rings are separated from each other by a small gap and all rings are capable of rotating in the same prescribed direction. A polishing pad is mounted on top of each ring, and a delivery tube is positioned at a distance above the polishing pads. The delivery tube further includes a tube handle and a tube surface, and the tube surface has a plurality of holes drilled in it for delivering slurry to the polishing pad surface. Each concentric ring of the polishing table is able to rotate such that all the rings have the same tangential polishing speed. Therefore a wafer surface can be more uniformly polished. Moreover, material having different density, roughness and chemical composition can be chosen to fabricate the polishing pads so that an even better polishing result can be obtained.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: September 12, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corp.
    Inventors: Ying-Chih Liu, Sen-Nan Lee
  • Patent number: 6101656
    Abstract: A wafer-cleaning device comprises a looped belt forming an enclosed region and a pair of rollers. Each roller occupies one end inside the enclosed region. Furthermore, a supporting structure located inside the enclosed region not only supports the rollers, but also maintains some tension on the belt. Thus, one portion of the belt is flat. The supporting structure is capable of supporting a wafer as well. In addition, a wafer-rotating device can be installed next to the edge of a wafer so that the wafer can rotate in a prescribed direction while the wafer surface is cleaned.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: August 15, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corp.
    Inventors: Sen-Nan Lee, Ying-Chih Liu
  • Patent number: 6022800
    Abstract: A method of reducing tungsten plug loss in processes for fabrication for silicon-based semiconductor devices that include a tungsten plug in a high aspect ratio contact hole. The invention provides a barrier layer prepared by first forming a conformal layer of titanium nitride by chemical vapor deposition. Afterward, another film of titanium nitride is supplied by plasma vapor deposition. The barrier layer comprises at least these two films, and tungsten is then deposited to at least fill the high aspect ratio film-coated contact hole. Upon removal of excess tungsten as by wet etch back, the tungsten plug remains essentially intact, and any plug loss is insignificant in comparison with the prior art.
    Type: Grant
    Filed: April 29, 1998
    Date of Patent: February 8, 2000
    Assignee: Worldwide Semiconductor Manufacturing Corporation
    Inventors: Wen-Yu Ho, Sen-Nan Lee, Sung Chun Hsieh, Hui-Lun Chen