Patents by Inventor Sen Xu

Sen Xu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220384445
    Abstract: The disclosure provides a method for manufacturing a memory and the memory. The method includes that a laminated structure is formed on a substrate, in which the laminated structure comprises sacrificial layers and supporting layers arranged alternately, a top layer of the laminated structure is a supporting layer, and a supporting layer between two sacrificial layers is provided with intermediate holes filled with a sacrificial material; capacitor holes penetrating through the laminated structure are formed; a first polar plates are formed on the hole walls and the hole bottoms of the capacitor holes; areas corresponding to the intermediate holes in the supporting layer located on the top layer of the laminated structure are removed to form capacitor opening holes, which exposes a sacrificial layer; and all the sacrificial layers and all the sacrificial material are removed through the capacitor opening holes.
    Type: Application
    Filed: November 2, 2021
    Publication date: December 1, 2022
    Inventors: Qiang WAN, Jun XIA, Kangshu ZHAN, Tao LIU, Penghui XU, Sen LI
  • Publication number: 20220360441
    Abstract: The application provides a data encryption and decryption method, device, storage medium, and encrypted file, and relates to the technical field of data processing. The method for data encryption includes: obtaining a first key, and performing an obfuscation operation on the first key and data to be encrypted to obtain obfuscation operation result data; obtaining a second key, and obtaining a first signature of the obfuscation operation result data according to the second key; obtaining a third key, and encrypting the first key, the data to be encrypted and the first signature using the third key to obtain a target ciphertext; obtaining a fourth key, and obtaining a second signature of the target ciphertext according to the fourth key; generating an encrypted file including the target ciphertext and the second signature. With the technical solutions of the application, security of data protection can be improved.
    Type: Application
    Filed: September 28, 2020
    Publication date: November 10, 2022
    Applicant: CHINA UNIONPAY CO., LTD.
    Inventors: Lin CHEN, Bin XU, Sen YANG
  • Publication number: 20220352305
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure and a semiconductor structure, and relates to the technical field of semiconductors. The manufacturing method includes: providing a base, wherein the base is provided with an active region; forming a gate layer on the base; forming isolation structures on a periphery of the gate layer, wherein in a direction away from the gate layer, each of the isolation structures at least includes a hollow portion and an isolation portion; forming an insulating structure on top surfaces of the isolation structures; forming contact plugs, wherein the contact plugs penetrate the insulating structure; an end of each of the contact plugs close to the base is electrically connected to the active region; each of the contact plugs is located on a side of each of the isolation structures away from the gate layer.
    Type: Application
    Filed: October 25, 2021
    Publication date: November 3, 2022
    Inventors: Qiang Wan, Kangshu Zhan, Jun Xia, Sen Li, Penghui Xu, Tao Liu
  • Publication number: 20220344156
    Abstract: Embodiment relates to a method for fabricating a semiconductor structure. The method includes: forming a first pattern on the first region and forming a second pattern on the second region, wherein the first pattern includes a plurality of first sub-patterns, a first gap is provided between adjacent two of the plurality of first sub-patterns, a width of the first gap is a first pitch, and wherein the second pattern includes a plurality of second sub-patterns, a second gap is provided between adjacent two of the plurality of second sub-patterns, a width of the second gap is a second pitch, and the second pitch is greater than the first pitch; forming a first mask layer on a sidewall of the first pattern, and forming a second mask layer on a sidewall of the second pattern; and removing the first pattern and the second pattern.
    Type: Application
    Filed: September 14, 2021
    Publication date: October 27, 2022
    Inventors: Kangshu ZHAN, Qiang WAN, Penghui XU, Tao LIU, Sen LI, Jun XIA
  • Publication number: 20220340834
    Abstract: A super-lubricity water lubricating additive, a super-lubricity water lubricant, a preparation method and application, wherein the additive is of a hollow spherical shell structure which includes at least one layer of spherical shell; the spherical shell sequentially includes a first polydopamine layer, a nanoparticle layer, a second polydopamine layer and an oxidized graphene layer from inside to outside, or a first polydopamine layer, a nanoparticle layer, a second polydopamine layer, a graphene layer and a third polydopamine layer from inside to outside; and nanoparticles of the nanoparticle layer are nano diamond, nano molybdenum disulfide or nano tungsten disulfide. The additive is prepared into a uniform aqueous solution to obtain the super-lubricity water lubricant. The additive can be easily adsorbed on a dual surface, and the nanoparticles released in a friction process cooperate with spherical oxidized graphene or graphene to form rolling friction so as to reduce frictional abrasion.
    Type: Application
    Filed: July 21, 2020
    Publication date: October 27, 2022
    Applicant: QINGDAO UNIVERSITY OF TECHNOLOGY
    Inventors: Qinglun CHE, Jianjun ZHANG, Sen LIANG, Ning CUI, Binjiang LV, Yang XU, Xinghua MA
  • Publication number: 20220337030
    Abstract: A drive circuit for a direct modulated laser and a direct modulated optical transmitter. The drive circuit includes a service data drive unit, a voltage configuration unit, a monitoring data modulation unit, and a monitoring current generation unit. Output terminals of the voltage configuration unit and the monitoring data modulation unit are connected to a same input terminal of the monitoring current generation unit. An output terminal of the service data drive unit is connected to a current sink interface of the monitoring current generation unit, and is suitable for connecting a direct modulated laser. In the technical solution, a low-speed monitoring data signal is mixed into an average optical power signal of a high-speed service data light wave from the direct modulated laser, then is extracted from the received optical signal by a remote optical receiver, enabling the drive circuit to be remotely monitored.
    Type: Application
    Filed: December 13, 2019
    Publication date: October 20, 2022
    Inventors: Hongchun Xu, Xueyong Zhang, Bo Zhang, Jing Wang, Zhiqiang Chen, Sen Hu, Jie Zhou
  • Patent number: 11476277
    Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 18, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
  • Patent number: 11469248
    Abstract: A three-dimensional (3D) NAND memory device is provided. The device comprises an alternating stack including a plurality of dielectric/conductive layer pairs each comprising a dielectric layer and a conductive layer. The device further comprises a conductive wall vertically penetrating through the alternating stack and extending in a horizontal direction, and a spacer layer on sidewalls of the conductive wall configured to insulate the conductive wall from the conductive layers of the alternating stack. The spacer layer comprises a first spacer sublayer having a first dielectric material, a second spacer sublayer having a second dielectric material, and a third spacer sublayer having a third dielectric material. The second spacer is sandwiched between the first spacer sublayer and the third spacer sublayer. A second k-value of the second dielectric material is higher than a first k-value of the first dielectric material and higher than a third k-value of the third dielectric material.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: October 11, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Lei Ding, Jing Gao, Chuan Yang, Lan Fang Yu, Ping Yan, Sen Zhang, Bo Xu
  • Patent number: 11465652
    Abstract: In one embodiment, a computing system of a vehicle may receive perception data associated with a scenario encountered by a vehicle while operating in an autonomous driving mode. The system may identify the scenario based at least on the perception data. The system may generate a performance metric associated with a vehicle navigation plan to navigate the vehicle in accordance with the identified scenario. In response to a determination that the performance metric associated with the vehicle navigation plan fails to satisfy one or more criteria for navigating the vehicle in accordance with the identified scenario, the system may trigger a disengagement operation related to disengaging the vehicle from the autonomous driving mode. The system may generate a disengagement record associated with the triggered disengagement operation. The disengagement record may include information associated with the identified scenario encountered by the vehicle related to the disengagement operation.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: October 11, 2022
    Assignee: Woven Planet North America, Inc.
    Inventors: Xiaojie Li, Sen Xu
  • Publication number: 20220317501
    Abstract: The present disclosure provides an array substrate, including a display region, and the display region includes driving circuit regions. The array substrate includes a first substrate, a gate driver on array (GOA) circuit and a pixel driving circuit respectively disposed on opposite sides of the first substrate and located in the driving circuit regions. The GOA circuit is connected with the pixel driving circuit through a plurality of via holes, so wiring regions of the GOA circuit and wiring regions of the pixel driving circuit can overlap in space, thereby reducing space occupied by a pixel display region and increasing a pixel aperture ratio.
    Type: Application
    Filed: October 29, 2020
    Publication date: October 6, 2022
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Bangqing Xiao, Sen Xu
  • Publication number: 20220317527
    Abstract: The present invention provides a display panel and a display device using the display panel. By connecting a plurality of second scan lines in parallel, resistance between output terminals of chips on film (COF) and first scan lines are reduced, and differences between output resistances of the COF corresponding to different first scan lines are reduced, so differences between signals in different first scan lines are reduced, and uneven display problems in existing display panels are solved.
    Type: Application
    Filed: November 5, 2020
    Publication date: October 6, 2022
    Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Bangqing XIAO, Sen XU
  • Publication number: 20220319849
    Abstract: A method for manufacturing a mask pattern includes the following operations. A pattern transfer layer, an etching stopping layer, a sacrificial layer and a hard mask layer that are stacked from bottom up are formed. The hard mask layer and the sacrificial layer are patterned to obtain sacrificial patterns which expose the etching stopping layer. Side wall structures are formed on the side walls of the sacrificial patterns. The sacrificial patterns are removed. Filling layers are formed between the side wall structures, and the etching selection ratio of the side wall structures to the filling layers is greater than 100. The side wall structures are removed to form an initial mask pattern. The etching stopping layer and the pattern transfer layer are etched based on the initial mask pattern to transfer a pattern of the initial mask pattern to the pattern transfer layer to obtain a target mask pattern.
    Type: Application
    Filed: October 12, 2021
    Publication date: October 6, 2022
    Inventors: Qiang WAN, Kangshu Zhan, Jun Xia, Sen Li, Penghui Xu, Tao Liu
  • Publication number: 20220319857
    Abstract: Embodiments of the present disclosure provide a patterning method and a semiconductor structure. The method includes: providing a substrate, wherein the substrate includes adjacent storage regions and peripheral circuit regions; forming, on the substrate, a pattern transfer layer, the pattern transfer layer having a plurality of first hard masks, wherein the first hard masks extend along a first direction and are spaced apart from each other; forming a barrier layer on the pattern transfer layer; forming, on the barrier layer, a plurality of second hard masks, the plurality of second hard masks extending along a second direction, wherein the second hard masks are spaced apart from each other, and the second hard masks are located in the storage regions and second hard masks close to the peripheral circuit regions have structural defects.
    Type: Application
    Filed: January 14, 2022
    Publication date: October 6, 2022
    Inventors: Qiang Wan, Jun Xia, Kangshu Zhan, Sen Li, Tao Liu, Penghui Xu
  • Publication number: 20220310402
    Abstract: The present disclosure provides a manufacturing method of a semiconductor structure, including: an insulating layer includes a first dielectric layer and a second dielectric layer, a protective layer covers an upper surface of the second dielectric layer and a bottom and sidewalls of the first trench; removing part of the protective layer to expose at least part of a surface of the second dielectric layer; removing the second dielectric layer by a first wet etching process, the first wet etching process has a first etch selectivity of a material of the second dielectric layer to that of the first dielectric layer; and removing the protective layer by a second wet etching process, the second wet etching process has a second etch selectivity of a material of the protective layer to that of the first dielectric layer, and the second etch selectivity is greater than the first etch selectivity.
    Type: Application
    Filed: January 21, 2022
    Publication date: September 29, 2022
    Inventors: Qiang WAN, Jun XIA, Kangshu ZHAN, Sen LI, Penghui XU, Tao LIU
  • Publication number: 20220310606
    Abstract: The present application provides a method for preparing a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductors. The method for preparing a semiconductor structure includes: providing a base; forming a support layer having capacitor holes and electric contact structures; forming a first dielectric layer in the capacitor holes, the first dielectric layer surrounding first intermediate holes; forming a first electrode layer in the first intermediate holes, the first electrode layer filling the first intermediate holes; removing part of the support layer to form second intermediate holes; forming a second dielectric layer in the second intermediate holes, the first dielectric layer and the second dielectric layer forming a dielectric layer; and, forming a second electrode layer on the dielectric layer.
    Type: Application
    Filed: October 15, 2021
    Publication date: September 29, 2022
    Inventors: Kangshu ZHAN, Qiang WAN, Penghui XU, Tao LIU, Sen LI, Jun XIA
  • Publication number: 20220309061
    Abstract: The embodiments of the present application provide a mining machine management method and system. The method includes: determining the number of target IPs corresponding to the mining machine written in configuration information and an update frequency of data, and starting the corresponding coroutine to collect the data from the mining machine corresponding to the target IPs based on the number of the target IPs and the update frequency of the data; and uploading the data to a local server, and uploading the data to a cloud server by the local server.
    Type: Application
    Filed: August 25, 2021
    Publication date: September 29, 2022
    Inventors: Xuejian Li, Haoran Chen, Sen Nie, Lin Sun, Yan Feng, Zhifu Wang, Fanghui Xu, Liang Chen
  • Publication number: 20220310607
    Abstract: A method for manufacturing a mask structure includes: patterning a sacrificial layer and a second dielectric layer, so as to form pattern structures each including a first pattern and a second pattern, and a width of a lower portion of the pattern structures is less than a width of a upper portion of the pattern structures; forming an initial mask pattern on sidewalls of each of the plurality of pattern structures; filling a first filling layer between adjacent initial mask patterns located on the sidewalls of different pattern structures; removing the second patterns and the initial mask pattern located on sidewalls of each of the plurality of second patterns; removing the first filling layer and the first patterns, so as to form first mask patterns; and forming second mask patterns on the first mask patterns.
    Type: Application
    Filed: September 23, 2021
    Publication date: September 29, 2022
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Qiang WAN, JUN XIA, Penghui XU, Tao LIU, Sen LI, Kangshu ZHAN
  • Publication number: 20220310393
    Abstract: A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.
    Type: Application
    Filed: January 14, 2022
    Publication date: September 29, 2022
    Inventors: Penghui XU, Qiang WAN, Tao LIU, Sen LI, Jun XIA, Kangshu ZHAN, Jinghao WANG
  • Publication number: 20220302127
    Abstract: The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a bit line located on the substrate; and a support layer located on the substrate, wherein the support layer includes a first support segment and a second support segment, the first support segment and the second support segment are both connected to the bit line, and the bit line is located between the first support segment and the second support segment.
    Type: Application
    Filed: February 8, 2022
    Publication date: September 22, 2022
    Inventors: Sen LI, Jun Xia, Kangshu Zhan, Tao Liu, Qiang Wan, Penghui Xu
  • Publication number: 20220290669
    Abstract: The present disclosure provides a pump body assembly, a heat exchange apparatus, a fluid machine and an operating method thereof. The pump body assembly includes a piston, a shaft, a piston sheath, and a cylinder. The shaft drives the piston to rotate and reciprocate within the piston sheath while rotating. The piston sheath is located in the cylinder, and a compression chamber is defined between an outer circumferential wall of the piston and an inner wall of the cylinder. A pressure relief recess is defined in the outer circumferential wall of the piston or the inner wall of the cylinder at a position corresponding to the compression chamber.
    Type: Application
    Filed: August 24, 2020
    Publication date: September 15, 2022
    Applicant: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAI
    Inventors: Mingzhu DONG, Yusheng HU, Huijun WEI, Jia XU, Zhongcheng DU, Liping REN, Sen YANG, Zhi LI, Peilin ZHANG, Shebing LIANG, Zhengliang SHI, Rongting ZHANG, Ning DING