Abstract: A reconfigurable crystal oscillator and a method for reconfiguring a crystal oscillator are provided. The reconfigurable crystal oscillator includes a transconductance circuit, a feedback resistor, a crystal tank, an input-end capacitor and an output-end capacitor. Both of the feedback resistor and the crystal tank are coupled between an input terminal and an output terminal of the transconductance circuit. The input-end capacitor is coupled to the input terminal of the transconductance circuit, and the output-end capacitor is coupled to the output terminal of the transconductance circuit. In particular, the transconductance circuit is configured to provide a transconductance, and when an operation mode of the reconfigurable crystal oscillator is switched, an input-end capacitance of the input-end capacitor and an output-end capacitance of the output-end capacitor are switched, respectively.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Abstract: A fast start-up crystal oscillator (XO) and a fast start-up method thereof are provided. The fast start-up XO may include a XO core circuit, a frequency synthesizer, and a fast start-up interfacing circuit, wherein the frequency synthesizer may include a voltage control oscillator (VCO) and a divider. The XO core circuit generates a XO signal having a XO frequency. The VCO generates a VCO clock having a VCO frequency, and the divider generates a divided clock having a divided frequency, wherein the VCO frequency is divided by a divisor of the divider to obtain the divided frequency. The fast start-up interfacing circuit transmits the divided clock to the XO core circuit, and then generates a reference clock having the XO frequency according to the XO signal. More particularly, the VCO frequency is calibrated according to the reference clock, in order to make the divided frequency approach the XO frequency.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range.

Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

Abstract: A harmonic-rejection modulation device is provided, which includes a phase splitter, a low pass filter, and a modulator. Based on a square wave, the phase splitter generates a plurality of unfiltered local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The low pass filter filters the high frequency components of the unfiltered local oscillating signals to generate a plurality of local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The modulator modulates a baseband signal with the local oscillating signals, wherein the third harmonics of the local oscillating signals are eliminated by the modulation process of the modulator. The invention also provides a method of modulating a baseband signal.

Abstract: A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock.

Abstract: A divide-by-N/(N+0.5) frequency divider is disclosed. Two pairs of flip-flops are respectively triggered by an input clock and an inverted input clock, and a frequency-dividing selector is used to select one output of the two pairs of flip-flops as frequency-divided output signal. Two latches are respectively triggered by the input clock and the inverted input clock, and a modulus selector is used to select one output of the two latches. A modulus logic circuit determines being in either N frequency-dividing mode or (N+0.5) frequency-dividing mode based on a modulus control signal. A frequency-dividing logic circuit receives output of the modulus logic circuit and an inverted frequency-divided output signal to swallow half the input clock per output cycle in the (N+0.5) frequency-dividing mode, therefore obtaining division resolution of half the input clock.

Abstract: A mobile system has a frequency synthesizer and an amplifier module coupled to the frequency synthesizer. The frequency synthesizer is controlled by frequency division data to generate a tuning signal with a frequency corresponding to a reference signal and the frequency division data. The mobile system provides an input signal based on the frequency of the tuning signal having a frequency spectrum corresponding to the frequency of the tuning signal. The amplifier module has a variable load circuit for providing an equivalent impedance, an amplifier circuit coupled to the variable load circuit for establishing an output signal corresponding to the input signal and the equivalent impedance of the variable load circuit, and a mapping circuit for modifying the equivalent impedance of the variable load circuit based on the frequency division data.

Abstract: A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sensing devices, and a reset control circuit. The sensing devices control the pulse generators based on signals received at corresponding first ends of the sensing devices. The inverting circuits generate signals to the first and second output ends of the phase-frequency detector based on signals received at corresponding first ends of the inverting circuits. The reset control circuit generates reset signals based on signals received at the first and second output ends of the phase-frequency detector.

Abstract: A power amplifier circuit amplifying an input signal to an output signal and a method thereof. The power amplifier circuit comprises a ramp controller, a current source, and a first amplification stage. The ramp controller receives an enable signal to generate a ramp signal. The current source is coupled to the ramp controller, produces a ramp current by the ramp signal. The first amplification stage is coupled to the current source, comprises a first supply voltage input coupled to a fixed supply voltage, and is biased by the ramp current to amplify the input signal such that an envelope of the output signal is a ramp.

Abstract: A mobile system has a frequency synthesizer and an amplifier module coupled to the frequency synthesizer. The frequency synthesizer is controlled by frequency division data to generate a tuning signal with a frequency corresponding to a reference signal and the frequency division data. The mobile system provides an input signal based on the frequency of the tuning signal having a frequency spectrum corresponding to the frequency of the tuning signal. The amplifier module has a variable load circuit for providing an equivalent impedance, an amplifier circuit coupled to the variable load circuit for establishing an output signal corresponding to the input signal and the equivalent impedance of the variable load circuit, and a mapping circuit for modifying the equivalent impedance of the variable load circuit based on the frequency division data.

Abstract: A phase-frequency detector generates output signals at a first and a second output end based on input signals received at a first and a second input end. The phase-frequency detector includes two latch circuits, two pulse generators, two inverting circuits, two sensing devices, and a reset control circuit. The sensing devices control the pulse generators based on signals received at corresponding first ends of the sensing devices. The inverting circuits generate signals to the first and second output ends of the phase-frequency detector based on signals received at corresponding first ends of the inverting circuits. The reset control circuit generates reset signals based on signals received at the first and second output ends of the phase-frequency detector.

Abstract: A harmonic-rejection modulation device is provided, which includes a phase splitter, a low pass filter, and a modulator. Based on a square wave, the phase splitter generates a plurality of unfiltered local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The low pass filter filters the high frequency components of the unfiltered local oscillating signals to generate a plurality of local oscillating signals having phase angles of 0°, 30°, 90°, 120°, 180°, 210°, 270° and 300°, respectively. The modulator modulates a baseband signal with the local oscillating signals, wherein the third harmonics of the local oscillating signals are eliminated by the modulation process of the modulator. The invention also provides a method of modulating a baseband signal.

Abstract: A power amplifier circuit amplifying an input signal to an output signal and a method thereof. The power amplifier circuit comprises a ramp controller, a current source, and a first amplification stage. The ramp controller receives an enable signal to generate a ramp signal. The current source is coupled to the ramp controller, produces a ramp current by the ramp signal. The first amplification stage is coupled to the current source, comprises a first supply voltage input coupled to a fixed supply voltage, and is biased by the ramp current to amplify the input signal such that an envelope of the output signal is a ramp.