Patents by Inventor Seng Guan Chow

Seng Guan Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804153
    Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: October 13, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Seng Guan Chow
  • Patent number: 10297556
    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: May 21, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 10163747
    Abstract: A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 10083916
    Abstract: A semiconductor device is made by forming a first conductive layer over a sacrificial carrier. A conductive pillar is formed over the first conductive layer. An active surface of a semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the conductive pillar. The carrier and adhesive layer are removed. A stress relief insulating layer is formed over the active surface of the semiconductor die and a first surface of the encapsulant. The stress relief insulating layer has a first thickness over the semiconductor die and a second thickness less than the first thickness over the encapsulant. A first interconnect structure is formed over the stress relief insulating layer. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The first and second interconnect structures are electrically connected through the conductive pillar.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: September 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Yaojian Yaojian
  • Patent number: 9893045
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: February 13, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon, Byung Tai Do, Linda Pei Ee Chua
  • Patent number: 9847253
    Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: December 19, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Publication number: 20170194228
    Abstract: A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 9666500
    Abstract: A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Kang Chen, Hin Hwa Goh, Yu Gu, Il Kwon Shim, Rui Huang, Seng Guan Chow, Jianmin Fang, Xia Feng
  • Publication number: 20170133330
    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.
    Type: Application
    Filed: January 25, 2017
    Publication date: May 11, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 9620557
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 11, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: 9607965
    Abstract: A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A plurality of semiconductor die is disposed over a portion of the substrate while leaving an open area of the substrate devoid of the semiconductor die. The open area of the substrate devoid of the semiconductor die includes a central area or interstitial locations among the semiconductor die. The semiconductor die are disposed around a perimeter of the substrate. An encapsulant is deposited over the semiconductor die and substrate. The substrate is removed and an interconnect structure is formed over the semiconductor die. By leaving the predetermined areas of the substrate devoid of semiconductor die, the warping effect of any mismatch between the CTE of the semiconductor die and the CTE of the encapsulant on the reconstituted wafer after removal of the substrate is reduced.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: March 28, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kian Meng Heng, Hin Hwa Goh, Jose Alvin Caparas, Kang Chen, Seng Guan Chow, Yaojian Lin
  • Patent number: 9559029
    Abstract: A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 31, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Il Kwon Shim, Yaojian Lin, Seng Guan Chow
  • Patent number: 9524955
    Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 9524938
    Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 9515016
    Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rui Huang, Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9508621
    Abstract: A semiconductor device has a stress relief buffer mounted to a temporary substrate in locations designated for bump formation. The stress relief buffer can be a multi-layer composite material such as a first compliant layer, a silicon layer formed over the first compliant layer, and a second compliant layer formed over the silicon layer. A semiconductor die is also mounted to the temporary substrate. The stress relief buffer can be thinner than the semiconductor die. An encapsulant is deposited between the semiconductor die and stress relief buffer. The temporary substrate is removed. An interconnect structure is formed over the semiconductor die, encapsulant, and stress relief buffer. The interconnect structure is electrically connected to the semiconductor die. A stiffener layer can be formed over the stress relief buffer and encapsulant. A circuit layer containing active devices, passive devices, conductive layers, and dielectric layers can be formed within the stress relief buffer.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: November 29, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Il Kwon Shim, Seng Guan Chow
  • Publication number: 20160276237
    Abstract: A semiconductor device has a semiconductor die. A first insulating layer is disposed over the semiconductor die. A first via is formed in the first insulating layer over a contact pad of the semiconductor die. A first conductive layer is disposed over the first insulating layer and in the first via. A second insulating layer is disposed over a portion of the first insulating layer and first conductive layer. An island of the second insulating layer is formed over the first conductive layer and within the first via. The first conductive layer adjacent to the island is devoid of the second insulating layer. A second conductive layer is disposed over the first conductive layer, second insulating layer, and island. The second conductive layer has a corrugated structure. A width of the island is greater than a width of the first via.
    Type: Application
    Filed: May 31, 2016
    Publication date: September 22, 2016
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Seng Guan Chow
  • Publication number: 20160111410
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Application
    Filed: December 16, 2015
    Publication date: April 21, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon, Byung Tai Do, Linda Pei Ee Chua
  • Publication number: 20160104731
    Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.
    Type: Application
    Filed: December 18, 2015
    Publication date: April 14, 2016
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Lee Sun Lim, Rui Huang, Xu Sheng Bao, Ma Phoo Pwint Hlaing
  • Patent number: RE48111
    Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 21, 2020
    Assignee: JCET Semiconductor (Shaoxing) Co. Ltd.
    Inventors: Reza A. Pagaila, Seng Guan Chow, Seung Uk Yoon, Byung Tai Do, Linda Pei Ee Chua