Patents by Inventor Seng Kim Ye

Seng Kim Ye has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194630
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate including multiple first electrical contacts and multiple bondable pillars. In some implementations, each bondable pillar, of the multiple bondable pillars, may be coupled to a corresponding first electrical contact, of the multiple first electrical contacts. The semiconductor device assembly may further include one or more dies coupled to the substrate and including multiple second electrical contacts. In some implementations, the semiconductor device assembly may include multiple wire bonds, with each wire bond, of the multiple wire bonds, bonding a second electrical contact, of the multiple second electrical contacts, to a bondable pillar, of the multiple bondable pillars.
    Type: Application
    Filed: December 6, 2023
    Publication date: June 13, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240194547
    Abstract: A variety of applications can include systems having packaged electronic devices. One or more of the packaged electronic devices can include a package substrate, having a first section and a second section with the second section elevated with respect to the first section, to support dies in the two sections. The first section can have a first top surface and a bottom surface with one or more layers of material between the first top surface and the bottom surface. The second section can include a second top surface and the bottom surface of the first section with the one or more layers of material of the first section extending horizontally from the first section. The second section can have one or more additional layers of material between the second top surface and the one or more layers of material of the first section extending horizontally from the first section.
    Type: Application
    Filed: November 22, 2023
    Publication date: June 13, 2024
    Inventors: Ling Pan, Seng Kim Ye, Hong Wan Ng, Kelvin Aik Boo Tan, See Hiong Leow
  • Publication number: 20240162206
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate and multiple first electrical contacts disposed on the substrate. The semiconductor device assembly may include a load switch coupled to the substrate and including a first outer surface facing the substrate and an opposing second outer surface facing away from the substrate. The load switch may include multiple second electrical contacts disposed on the second outer surface. The semiconductor device assembly may include multiple wire bonds electrically coupling the load switch to the substrate, wherein each wire bond electrically couples a corresponding first electrical contact, of the multiple first electrical contacts, to a corresponding second electrical contact, of the multiple second electrical contacts.
    Type: Application
    Filed: November 7, 2023
    Publication date: May 16, 2024
    Inventors: Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240162207
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor package includes a substrate, a semiconductor die disposed on the substrate, and a passive electronic component disposed on the semiconductor die.
    Type: Application
    Filed: October 30, 2023
    Publication date: May 16, 2024
    Inventors: Kelvin Aik Boo TAN, Hong Wan NG, See Hiong LEOW, Seng Kim YE, Ling PAN
  • Publication number: 20240128254
    Abstract: Stacked semiconductor die assemblies with support members and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a package substrate, a first semiconductor die attached to the package substrate, and a plurality of support members also attached to the package substrate. The plurality of support members can include a first support member and a second support member disposed at opposite sides of the first semiconductor die, and a second semiconductor die can be coupled to the support members such that at least a portion of the second semiconductor die is over the first semiconductor die.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye
  • Publication number: 20240128163
    Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.
    Type: Application
    Filed: December 27, 2023
    Publication date: April 18, 2024
    Inventors: Hong Wan Ng, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye, Kelvin Tan Aik Boo
  • Publication number: 20240128182
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a base layer, a dielectric interposer coupled to the base layer and including a first outer surface facing the base layer and an opposing second outer surface facing away from the base layer and spaced apart from the first outer surface in a direction, a first electrical-connection cut-in in the second outer surface that extends, in the direction, toward the first outer surface, and one or more first electrical connections disposed within the first electrical-connection cut-in such that at least a portion of the one or more first electrical connections does not extend, in the direction, beyond the second outer surface.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 18, 2024
    Inventors: Chin Hui CHONG, Seng Kim YE, Hong Wan NG, Kelvin Aik Boo TAN
  • Patent number: 11942460
    Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 26, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Kelvin Tan Aik Boo, Chin Hui Chong, Hem P. Takiar, Seng Kim Ye
  • Patent number: 11929351
    Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: March 12, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Publication number: 20240072022
    Abstract: Semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having an inner surface, a die stack carried by the inner surface, and a stacked capacitor device carried by the inner surface adjacent to the die stack. The die stack can include one or more semiconductor dies, each of which can be electrically coupled to the inner surface by one or more bond wires and/or solder structures. The stacked capacitor device can include a first capacitor having a lower surface attached to the inner surface of the package substrate, a interposer having a first side attached to an upper surface of the first capacitor, and a second capacitor attached to a second side of the interposer opposite the first side.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20240071869
    Abstract: A semiconductor device assembly including a substrate; a first split via including a first via land that is disposed on a surface of the substrate and that has a first footprint with a half-moon shape with a first radius of curvature, and a first via that passes through the substrate and that has a second radius of curvature, wherein the first via is disposed within the first footprint; and a second split via including a second via land that is disposed on the surface of the substrate and that has a second footprint with the half-moon shape with the first radius of curvature, and a second via that passes through the substrate and that has the second radius of curvature, wherein the second via is disposed within the second footprint, wherein the first and second via lands are disposed entirely within a circular region having the first radius of curvature.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Tan Aik Boo, Ling Pan, See Hiong Leow
  • Publication number: 20240071980
    Abstract: Stacked semiconductor devices, and related systems and methods, are disclosed herein. In some embodiments, the stacked semiconductor device includes a package substrate having at least a first layer and a second layer, an interconnect extending through the package substrate, a stack of dies carried by the package substrate, and one or more wirebonds electrically coupling the stack of dies to package substrate. Each of the layers of the package substrate can include a section of the interconnect with a frustoconical shape. Each of the sections can be directly coupled together. Further, the section in an uppermost layer of the package substrate is exposed at an upper surface of the package substrate. The wirebonds can be directly coupled to the exposed surface of the uppermost section.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240071880
    Abstract: This document discloses techniques, apparatuses, and systems relating to a package substrate for a semiconductor device. A semiconductor device assembly is described that includes a packaged semiconductor device having one or more semiconductor dies coupled to a package-level substrate. The package-level substrate has a first surface at which first contact pads are disposed in a first configuration. The packaged semiconductor device is coupled with an additional package-level substrate that includes a second surface having second contact pads disposed in the first configuration and a third surface having third contact pads disposed in a second configuration different from the first configuration. The additional package-level substrate includes circuitry coupling the second contact pads the third contact pads to provide connectivity at the third contact pads. In doing so, an adaptively compatible semiconductor device may be assembled.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Seng Kim Ye, Kelvin Tan Aik Boo, Hong Wan Ng, Chin Hui Chong
  • Publication number: 20240072024
    Abstract: Modular systems in packages, and associated devices, systems, and methods, are disclosed herein. In one embodiment, a system comprises a main module package and an upper module package. The main module package includes a first substrate and a first electronic device mounted on a first side of the first substrate. The upper module package includes a second substrate and one or more second electronic devices mounted on a first side of the second substrate. The second substrate includes a cavity at a second side of the second substrate opposite the first side, and the upper module package is mountable on the first side of the first substrate of the main module package such that the first electronic device is positioned within the cavity and the second substrate generally surrounds at least a portion of a perimeter of the first electronic device.
    Type: Application
    Filed: August 27, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Hong Wan Ng, Seng Kim Ye, Chin Hui Chong
  • Publication number: 20240074048
    Abstract: A semiconductor device assembly includes a semiconductor die, a substrate carrying the semiconductor die, and a printed circuit board (PCB) coupled to the substrate. The PCB includes a primary conductive layer including a first surface of the substrate and a first solder mask layer coupled to the first surface. The substrate also includes a secondary conductive layer including a second surface of the substrate and a second solder mask layer coupled to the second surface. The substrate further includes an inner conductive layer positioned between the primary layer and the secondary layer, where the inner layer includes a bond pad positioned at the end of an opening that extends from the first solder mask layer through the primary layer to the bond pad of the inner layer. By attaching a solder ball to the bond pad of the inner layer, standoff height is reduced.
    Type: Application
    Filed: August 23, 2022
    Publication date: February 29, 2024
    Inventors: Ling Pan, Hong Wan Ng, Kelvin Tan Aik Boo, Seng Kim Ye, See Hiong Leow
  • Publication number: 20240071886
    Abstract: Methods, systems, and devices for multi-chip package with enhanced conductive layer adhesion are described. In some examples, a conductive layer (e.g., a conductive trace) may be formed above a substrate. An integrated circuit may be bonded to the conductive layer and an encapsulant may be deposited at least between the integrated circuit and the conductive layer. In some examples, one or more surface features or one or more recesses may be formed on or within the conductive layer and the encapsulant may adhere to the surface features or recesses.
    Type: Application
    Filed: August 30, 2022
    Publication date: February 29, 2024
    Inventors: Hong Wan Ng, Seng Kim Ye, Kelvin Aik Boo Tan, Chin Hui Chong
  • Publication number: 20240071990
    Abstract: A semiconductor device assembly including a semiconductor device having a plurality of pillars disposed on a backside surface of the semiconductor device; and a substrate, including: a solder mask layer disposed on a front side surface of the substrate, a plurality of extended bond pads disposed on the frontside surface of the substrate and surrounded by the solder mask layer, the plurality of extended bond pads each having a top surface higher than a top surface of the solder mask layer, and wherein the semiconductor device is directly attached to the substrate by bonding each of the plurality of pillars of the semiconductor device to the top surface of a corresponding one of the plurality of extended bond pads with a solder connection.
    Type: Application
    Filed: August 25, 2022
    Publication date: February 29, 2024
    Inventors: Kelvin Tan Aik Boo, Seng Kim Ye, Hong Wan Ng, Ling Pan, See Hiong Leow
  • Publication number: 20240063201
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly may include a substrate, a flip chip die electrically coupled to the substrate via a plurality of electrical connections, and a non-conductive film disposed between the flip chip die and the substrate. The non-conductive film may surround the plurality of electrical connections and mechanically couple the flip chip die to the substrate.
    Type: Application
    Filed: August 17, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong LEOW, Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, Ling PAN
  • Publication number: 20240063135
    Abstract: Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Hong Wan NG, Seng Kim YE, Kelvin Aik Boo TAN, See Hiong LEOW, Ling PAN
  • Publication number: 20240063168
    Abstract: Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.
    Type: Application
    Filed: August 16, 2022
    Publication date: February 22, 2024
    Inventors: See Hiong Leow, Hong Wan NG, Seng Kim Ye, Kelvin Aik Boo Tan, Ling Pan