Patents by Inventor Seng-Sooi Lim

Seng-Sooi Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7327043
    Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: February 5, 2008
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Allen Seng Sooi Lim, Maurice O. Othieno
  • Publication number: 20060043565
    Abstract: A method wherein a substrate with plating tails is formed or otherwise provided, such as by performing a conventional electroplating process. Subsequently, a laser is used to remove some or all of the plating tails or a portion of some or all of the plating tails. If portions or remnants of the plating tails are to remain, the plating tails can be connected to ground. By connecting the remnants of the plating tails to ground, an electrical performance enhancement can be realized. Specifically, additional shielding in the package can be provided. Furthermore, the plating tails can be specifically designed to enhance the amount of shielding they provide.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 2, 2006
    Inventors: Chok Chia, Seng-sooi Lim, Wee Liew
  • Patent number: 6519844
    Abstract: An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: February 18, 2003
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Seng Sooi Lim, Chok J. Chia
  • Patent number: 6512293
    Abstract: A method and apparatus for providing a ball grid array assembly formed from interlocking ball grid array packages is disclosed. Each of the ball grid array packages has interlocking edge features for mechanical connection, whereby joining the plurality of ball grid array packages via the interlocking edge features forms the interlocking ball grid array assembly. The interlocking ball grid array assembly may then be mounted on a PC board as a single unit.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: January 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Wee K. Liew
  • Patent number: 6492253
    Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: December 10, 2002
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Patrick Variot
  • Patent number: 6225695
    Abstract: One aspect of the invention relates to a flip-chip semiconductor package. In one version of the invention, the flip-chip semiconductor package includes a package substrate having an upper surface, a lower surface and a plurality of conductive traces, the upper surface having an upper plurality of electrical contacts coupled to the conductive traces, the lower surface having a lower plurality of electrical contacts coupled to the conductive traces, the lower plurality of electrical contacts being attachable to electrical contacts on a printed circuit board; a semiconductor die having an active surface and a non-active surface, the active surface having a plurality of circuit elements and a plurality of bond pads formed thereon, the bond pads being attached to the upper plurality of electrical contacts by solder bumps, the non-active surface having a plurality of grooves formed thereon; and a heat sink attached to the non-active surface of the semiconductor die.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: May 1, 2001
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Maniam Alagaratnam
  • Patent number: 6114189
    Abstract: One aspect of the invention relates to a semiconductor substrate. In one version of the invention, a semiconductor substrate includes a package substrate having first and second surfaces with conductive traces formed thereon and structures for providing electrical connection between selected conductive traces, a die attach area on the first surface of the package substrate adapted to provide physical connection to a semiconductor die, the die attach area having conductive contacts for providing electrical connection between the die and conductive traces on the first surface, a package frame, at least one substrate strap which connects the package substrate to the package frame, the substrate strap being formed integrally with the package substrate and the package frame.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: September 5, 2000
    Assignee: LSI Logic Corp.
    Inventors: Chok J. Chia, Seng-Sooi Lim, Qwai H. Low
  • Patent number: 6081997
    Abstract: A system and method are presented for forming a grid array device package around an integrated circuit. The integrated circuit includes multiple I/O pads on an underside surface, and an upper surface of a substrate includes a corresponding set of bonding pads. The substrate also has an opening (i.e., a hole) extending therethrough and preferably substantially in the center of the set of bonding pads. Solder bumps formed upon the I/O pads of the integrated circuit are placed in direct contact with corresponding members of the set of bonding pads, then heated until they flow in a C4 connection method. Following C4 connection of the I/O and bonding pads, the substrate and the attached integrated circuit are positioned within a mold cavity formed between two mold sections, and a liquid encapsulant material is injected through the opening of the substrate such that the encapsulant fills the mold cavity. The coupled I/O and bonding pads are enveloped by the liquid encapsulant.
    Type: Grant
    Filed: August 14, 1997
    Date of Patent: July 4, 2000
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Maniam Alagaratnam
  • Patent number: 6054767
    Abstract: A programmable substrate and a method of making a programmable substrate for use with array-type packages, including Ball Grid Arrays(BGA), Pin Grid Arrays (PGA) and Column Grid Arrays (CGA) includes a nonconductive programmable substrate with a cavity in the top of the substrate. The cavity is sized to receive an integrated circuit (IC) die. An array of electrically conductive vias pass through the substrate. A plurality of electrical traces are formed on the top of the substrate. The traces extend radially from an edge of the die cavity to the periphery of the substrate so as to pass between and near the vias. Each trace is electrically connected to a pad of the IC die by a wire bond. Each via is connected on a bottom surface of the substrate to a solder ball, pin, or other means for electrically and mechanically attaching the substrate to a printed circuit board. The traces are programmably connected to a selected via, e.g.
    Type: Grant
    Filed: January 13, 1998
    Date of Patent: April 25, 2000
    Assignee: LSI Logic Corp.
    Inventors: Chok J. Chia, Seng-Sooi Lim, Patrick Variot
  • Patent number: 6040632
    Abstract: A multiple-sized integrated circuit (IC) die and a method of making a multiple-sized IC die includes forming a plurality of IC dies on a semiconductor wafer. Each IC die has multiple rows of bonding pads around its periphery. Adjacent bonding pads on separate rows of each IC die are electrically connected together so that attachment to any one of the connected bond pads yields the same result. A plurality of scribe streets separate each IC die on the wafer, with the scribe street defining the width between each IC die. Rows of bonding pads reside in the scribe street area. Different rows of bonding pads may be selectively removed from the IC die by scribing the wafer so as to include one or more of the rows of bonding pads, thereby allowing one IC die design to have multiple sizes. An IC die separated from the wafer may still be sized smaller as long as there remain at least two rows of bonding pads around the periphery.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: March 21, 2000
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Seng-Sooi Lim
  • Patent number: 6002169
    Abstract: A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155).
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: December 14, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Owai H. Low
  • Patent number: 5981311
    Abstract: A method of electroplating a high density integrated circuit (IC) substrate using a removable plating bus including the steps of providing an IC substrate made of nonconductive material having a plurality of conductive traces formed on its surface. Attaching a removable plating bus to the IC substrate, covering the plurality of conductive traces. Forming through holes (or vias) in predetermined locations. The holes going through the removable plating bus and IC substrate, exposing edges of selected conductive traces in the holes. Plating the through holes with a conductive material (such as copper) that electrically connects the removable plating bus to the exposed edges of the traces in the holes. Coating the IC substrate (including the removable plating bus) with plating resist and selectively removing portions of the removable plating bus, along with the plating resist, to expose selected areas of traces on the IC substrate that require plating.
    Type: Grant
    Filed: June 25, 1998
    Date of Patent: November 9, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng Sooi Lim, Patrick Variot
  • Patent number: 5973397
    Abstract: A semiconductor device and fabrication method are presented which advantageously combine TAB and wire bonding techniques to increase integrated circuit I/O pad density. The semiconductor device includes an integrated circuit, a substrate, and a carrier film (i.e., a TAB tape). The integrated circuit has a set of input/output (I/O) pads arranged upon an upper surface. The substrate has a die cavity within an upper surface and a set of bond traces arranged about the die cavity. An underside surface of the integrated circuit is attached to the substrate within the die cavity. The carrier film is positioned over the upper surface of the substrate such that the upper surface of the integrated circuit is exposed through a die aperture and portions of the members of the set of bond traces are exposed through corresponding members of a set of bond trace apertures.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Chok J. Chia, Seng-Sooi Lim
  • Patent number: 5973393
    Abstract: An apparatus and method for packaging an integrated circuit having a semiconductor die with electronic circuitry disposed thereon includes lead frames for mounting thereon solder balls of a ball grid array packaging structure. In one embodiment, the semiconductor die is coupled to conductors of the lead frame via gold wires attached to both the semiconductor die and the lead frame. The lead frame is encapsulated in plastic with apertures disposed therein for exposing upper and lower portions of conductors of the lead frame. The apertures are filled with solder balls to contact both the upper and lower portions of the lead frame conductors. Solder balls on the top of one integrated circuit package may be connected to mating solder balls on the bottom of another integrated circuit package, and so on, thereby achieving multiple stacking of integrated circuit packages.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: October 26, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Qwai H. Low
  • Patent number: 5927505
    Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: July 27, 1999
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Maniam Alagaratnam
  • Patent number: 5744084
    Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: April 28, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim, Maniam Alagaratnam
  • Patent number: 5643835
    Abstract: A process of mounting a semiconductor device and leadframe to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
    Type: Grant
    Filed: February 16, 1996
    Date of Patent: July 1, 1997
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim
  • Patent number: 5594626
    Abstract: A dambar-less leadframe is sandwiched between two printed circuit boards (PCBs). The PCBs form a major portion of the package body, and isolate the leadframe leads from plastic molding compound. In one embodiment, an upper PCB (substrate) is formed as a ring, having an opening containing a heat sink element. A lower PCB is also formed as a ring, and has a smaller opening for receiving a die. The back face of the die is mounted to the heat sink. The exposed front face of the die is wire bonded to inner ends of conductive traces on the exposed face of the lower PCB. The outer ends of the traces are electrically connected to the leadframe leads by plated-through vias extending through the two PCBs. The plated-through vias additionally secure the sandwich structure together. Plastic molding compound is injection/transfer molded over the front face of the die and the bond wires, forming a partially-molded package. In another embodiment, the upper PCB is a solid planar element.
    Type: Grant
    Filed: May 2, 1995
    Date of Patent: January 14, 1997
    Assignee: LSI Logic Corporation
    Inventors: Michael D. Rostoker, Chok J. Chia, Seng-Sooi Lim
  • Patent number: 5568683
    Abstract: A removable heatsink assembly comprised of a heatsink unit and a heatspreader is provided. The heatsink unit has at least one fin and a coupling collar for radiating heat away from a packaged electronic device. The heatspreader includes a platform attached to an inner collar in thermal contact with the packaged electronic device. The platform has one or more tabs suitable for mating with one or more flanges located on the coupling collar of the heatsink unit. Coupling grooves within the flanges engage the platform of the heatspreader when the flanges are mated with the heatspreader tabs and the heatsink is turned. The heatsink can therefore be quickly and conveniently attached to or removed from the heatspreader. The present invention thus permits a wide variety of different heatsinks to be interchangeably used with a single heatspreader attached to an electronic device package.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 29, 1996
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Manian Alagaratnam, Qwai H. Low, Seng-Sooi Lim
  • Patent number: 5521427
    Abstract: A packaged semiconductor device, leadframe for making same, and method of mounting same to a printed circuit board are described. The device has a body, and a plurality of leads extending from the body. One or more alignment features are formed on the exterior of the package body, for maintaining precise alignment of the device with respect to a printed wiring board. The alignment feature is a tab formed as part of portion of the leadframe external to the package body. The tab may have various shapes, and may be provided with a hole for registering with a pin on an underlying substrate, such as a printed wiring board. The pin and the tab may be electrically connected.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: May 28, 1996
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Seng-Sooi Lim