Patents by Inventor Seng Tan

Seng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR DEVICES WITH MEMORY CELLS
    Publication number: 20210217859
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly, to semiconductor devices having memory cells for multi-bit programming and methods of forming the same. The present disclosure provides a semiconductor device including an isolation region disposed on a substrate, a pair of diffusion structures disposed upon the isolation region, a dielectric layer that covers side surfaces of the diffusion structures, and a gate structure disposed on the dielectric layer and between the diffusion structures, where the gate structure is electrically coupled to the diffusion structures.
    Type: Application
    Filed: January 13, 2020
    Publication date: July 15, 2021
    Inventors: WEI CHANG, ENG HUAT TOH, SHYUE SENG TAN
  • Sensors having resistive elements
    Patent number: 11063158
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 13, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • Semiconductor devices with ion-sensitive field effect transistor
    Patent number: 11054387
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices integrated with an ion-sensitive field-effect transistor (ISFET) and methods of forming the same. The semiconductor device may include a substrate, a reference gate structure disposed above the substrate, a floating gate structure disposed above the substrate and adjacent to the reference gate structure, where the reference gate structure is electrically coupled to the floating gate structure, and a dielectric layer disposed between the reference gate structure and the floating gate structure.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: July 6, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Eng Huat Toh
  • Logic gate devices and methods of forming a logic gate device
    Patent number: 11050426
    Abstract: According to various embodiments, a logic gate device includes a transistor, a first resistor, a second resistor and a third resistor. The first resistor is connected between a first input terminal of the logic gate device and a gate terminal of the transistor. The second resistor is connected between a second input terminal of the logic gate device and the gate terminal. The third resistor is connected between a voltage supply terminal and a first terminal of the transistor. The logic gate device is configured to generate an output voltage at the first terminal based on input voltages received at the first input terminal and the second input terminal.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 29, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Shyue Seng Tan
  • SENSORS HAVING RESISTIVE ELEMENTS
    Publication number: 20210184059
    Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.
    Type: Application
    Filed: December 16, 2019
    Publication date: June 17, 2021
    Inventors: LANXIANG WANG, ENG HUAT TOH, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK
  • ON-CHIP TEMPERATURE SENSING WITH NON-VOLATILE MEMORY ELEMENTS
    Publication number: 20210164845
    Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Bin Liu, Eng Huat Toh, Shyue Seng Tan, Kiok Boone Elgin Quek
  • NON-VOLATILE MEMORY ELEMENTS WITH ONE-TIME OR MULTIPLE-TIME PROGRAMMABILITY
    Publication number: 20210167069
    Abstract: Structures for a non-volatile memory and methods of forming such structures. A gate electrode and a gate dielectric layer are formed over an active region with the gate dielectric layer between the gate electrode and the active region. A first doped region is formed in the active region, a second doped region is formed in the active region, and a source line is coupled to the second doped region. The first doped region is positioned in the active region at least in part beneath the gate dielectric layer, and the second doped region is positioned in the active region adjacent to the first doped region. The first doped region has a first conductivity type, and the second doped region has a second conductivity type opposite to the first conductivity type.
    Type: Application
    Filed: December 2, 2019
    Publication date: June 3, 2021
    Inventors: Desmond Jia Jun Loy, Eng Huat Toh, Sriram Balasubramanian, Shyue Seng Tan
  • NON-VOLATILE MEMORY BIT CELLS WITH NON-RECTANGULAR FLOATING GATES
    Publication number: 20210159234
    Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.
    Type: Application
    Filed: November 26, 2019
    Publication date: May 27, 2021
    Inventors: Lanxiang Wang, Shyue Seng Tan, Kiok Boone Elgin Quek, Xinshu Cai, Eng Huat Toh
  • HALL SENSORS WITH A THREE-DIMENSIONAL STRUCTURE
    Publication number: 20210135095
    Abstract: Structures for a Hall sensor and methods of forming a structure for a Hall sensor. The structure includes a semiconductor body having a top surface and a sloped sidewall defining a Hall surface that intersects the top surface. The structure further includes a well in the semiconductor body and multiple contacts in the semiconductor body. The well has a section positioned in part beneath the top surface and in part beneath the Hall surface. Each contact is coupled to the section of the well beneath the top surface of the semiconductor body.
    Type: Application
    Filed: November 1, 2019
    Publication date: May 6, 2021
    Inventors: Ping Zheng, Bin Liu, Eng Huat Toh, Shyue Seng Tan, Ruchil Kumar Jain, Kiok Boone Elgin Quek
  • MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE
    Publication number: 20210135101
    Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Desmond Jia Jun LOY, Eng Huat TOH, Shyue Seng TAN, Steven SOSS
  • Memory device and a method for forming the memory device
    Patent number: 10991704
    Abstract: A memory device may include a substrate, a first gate structure, a mask and a second gate structure. The substrate may include a source region and a drain region at least partially arranged within the substrate, and a channel region arranged between the source region and the drain region. The first gate structure may be at least partially arranged over the channel region, and may include a top surface that may be substantially flat. The mask may be at least partially arranged over the top surface of the first gate structure. The second gate structure may be at least partially arranged over the mask and at least partially arranged adjacent to the first gate structure.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 27, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Xinshu Cai, Shyue Seng Tan, Khee Yong Lim, Kiok Boone Elgin Quek
  • Bis(aniline) compounds containing multiple substituents with carbon-carbon triple-bonded groups
    Patent number: 10988437
    Abstract: The invention relates to bis(aniline) compounds containing multiple arylethynyl, alkylethynyl, ethynyl groups or their combinations, processes of making such compounds and materials comprising such compounds. Such, bis(aniline) compounds preferably comprise multiple phenylethynyl (PE) groups, i.e. 2-4 PE moieties. Such compounds are useful monomers for the preparation of polyimides, polyamides and poly(amide-imides) whose post-fabrication crosslinking chemistry (i.e. reaction temperature) can be controlled by the number of PE per repeat unit as well as finding utility in thermosetting matrix resins, 3D printable resins, and as high-carbon-content precursors to carbon-carbon composites.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: April 27, 2021
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Loon-Seng Tan, Zhenning Yu
  • Multi-rate transceiver circuitry
    Patent number: 10958411
    Abstract: Techniques to operate circuitry in an integrated circuit are provided. The circuitry may include rate detection circuitry, receiver circuitry, and configuration circuitry. The receiver circuitry may receive a data stream with an arbitrary data rate. The rate detection circuitry may receive a reference clock signal that is associated with the received data stream. The rate detection circuitry determines the frequency of the reference clock signal such that an appropriate clock signal may be generated for the receiver circuitry. The receiver clock signal may be generated by clock generation circuitry that is coupled to the rate detection circuitry. The configuration circuitry may accordingly configure the receiver circuitry based at least on the determined frequency of the reference clock signal so that the receiver circuitry may operate at the arbitrary data rate.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: March 23, 2021
    Assignee: Altera Corporation
    Inventors: Boon Hong Oh, Chee Seng Tan, Chau Perng Chin
  • Integrated circuits with resistive non-volatile memory cells and methods for producing the same
    Patent number: 10950661
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a memory cell, wherein the memory cell includes a transistor having a source and a drain, a first resistive unit in electrical communication with the source, and a second resistive unit in electrical communication with the drain. The first resistive unit includes a first bottom electrode, a first top electrode, and a first resistive element positioned between the first bottom electrode and the first top electrode. The second resistive unit includes a second bottom electrode, a second top electrode, and a second resistive element positioned between the second bottom electrode and the second top electrode.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: March 16, 2021
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Semiconductor device with a through-substrate via hole having therein a capacitor and a through-substrate via conductor
    Patent number: 10950689
    Abstract: A semiconductor device 100 comprising a substrate 102 having a through-substrate via hole 106, the through-substrate via hole 106 having formed therein: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116. A method of forming a semiconductor device 100, the semiconductor device 100 comprising a through-substrate via hole 106, the method comprising forming, in the through-substrate via hole 106: a first capacitor electrode layer 110a and a second capacitor electrode layer 110b, and a dielectric material layer 112 disposed between the first capacitor electrode layer 110a and the second capacitor electrode layer 110b; and a through-substrate via conductor 116.
    Type: Grant
    Filed: September 21, 2016
    Date of Patent: March 16, 2021
    Assignee: Nanyang Technological University
    Inventors: Ye Lin, Chuan Seng Tan
  • MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE
    Publication number: 20210074916
    Abstract: A memory device may include a first conductor and a second conductor; a switching layer arranged between the first conductor and the second conductor, and one or more magnetic layers. The switching layer may be configured to have a switchable resistance in response to a change in voltage between the first conductor and the second conductor. The one or more magnetic layers may be arranged such that the one or more magnetic layers provide a magnetic field through the switching layer.
    Type: Application
    Filed: September 10, 2019
    Publication date: March 11, 2021
    Inventors: Jianxun SUN, Juan Boon TAN, Tu Pei CHEN, Shyue Seng TAN
  • SENSOR AND METHOD OF FORMING THE SAME
    Publication number: 20210066514
    Abstract: A sensor may be provided, including a substrate having a first semiconductor layer, a second semiconductor layer, and a buried insulator layer arranged between the first semiconductor layer and the second semiconductor layer. The sensor may further include a photodiode arranged in the first semiconductor layer; and a quenching resistive element electrically connected in series with the photodiode. The quenching resistive element is arranged in the second semiconductor layer, and the quenching resistive element is arranged over the photodiode but separated from the photodiode by the buried insulator layer.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Lanxiang WANG, Shyue Seng TAN, Eng Huat TOH
  • MEMORY CELLS WITH EXTENDED ERASE GATE, AND PROCESS OF FABRICATION
    Publication number: 20210066324
    Abstract: A flash memory device is provided. The device comprises a substrate and a source region in the substrate. A first gate stack is positioned above the substrate and adjacent to the source region. A dual function gate structure having an upper portion and a lower portion is positioned above the source region. The upper portion of the dual function gate structure overlaps the first gate stack and the lower portion is adjacent to the first gate stack. A second gate is positioned above the substrate on an opposite side of the first gate stack from the dual function gate. A drain region is in the substrate adjacent to the second gate.
    Type: Application
    Filed: August 28, 2019
    Publication date: March 4, 2021
    Inventors: XINSHU CAI, SHYUE SENG TAN, KIOK BOONE ELGIN QUEK, ENG HUAT TOH
  • SEMICONDUCTOR DEVICES WITH ION-SENSITIVE FIELD EFFECT TRANSISTOR
    Publication number: 20210055256
    Abstract: The present disclosure generally relates to semiconductor devices, and more particularly to semiconductor devices integrated with an ion-sensitive field-effect transistor (ISFET) and methods of forming the same. The semiconductor device may include a substrate, a reference gate structure disposed above the substrate, a floating gate structure disposed above the substrate and adjacent to the reference gate structure, where the reference gate structure is electrically coupled to the floating gate structure, and a dielectric layer disposed between the reference gate structure and the floating gate structure.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Inventors: XINSHU CAI, SHYUE SENG TAN, ENG HUAT TOH
  • MEMORY DEVICE AND A METHOD FOR FORMING THE MEMORY DEVICE
    Publication number: 20210043637
    Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 11, 2021
    Inventors: Desmond Jia Jun LOY, Eng Huat Toh, Bin Liu, Shyue Seng Tan