Patents by Inventor Senji Shoji

Senji Shoji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4095253
    Abstract: A single in-line, high power, resin-packaged semiconductor device having a plurality of external leads disposed in parallel to each other and projecting from one side surface of a resin-molded package, wherein a heat sink fin mounting plate is formed in unitary structure with a plate for carrying a semiconductor pellet and arranged to project from a recessed portion of the opposite side surface of the resin-molded package and a heat sink fin has one end bent in U-shape and caulked on the fin mounting plate and the remaining portion overlapping one principal surface of the resin-molded package. The projection of the heat sink fin from the resin-molded package can be reduced to enable the device to be assembled in compact electronic instruments or devices. Heat dissipation efficiency can also be improved by mounting the semiconductor device on a chassis with the heat sink fin brought in contact with the chassis.
    Type: Grant
    Filed: November 23, 1976
    Date of Patent: June 13, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Masayoshi Yoshimura, Keizo Otsuki, Senji Shoji, Tomio Yamada, Ichio Shimizu, Yuji Arai
  • Patent number: 3946425
    Abstract: In a semiconductor integrated circuit device in which a plurality of regions each having a semiconductor element such as a PN junction diode and a transistor are isolated electrically from one another by PN junctions formed between the respective regions and a semiconductor isolation region, gold is introduced into the regions having the semiconductor elements and the isolation region while at least one diffused region heavily doped, for example, with phosphorus is formed in the isolation region adjacent to the region having the PN junction diode or the transistor thereby to prevent the breakdown voltage of the backwardly biased PN junction in the diode or the transistor from decreasing. Further by surrounding all the transistors, at least in one of which gold is diffused, formed in one integrated circuit with heavily doped N.sup.+-type regions an integrated circuit with transistors having a small variation in current amplification factor is obtained.
    Type: Grant
    Filed: May 14, 1974
    Date of Patent: March 23, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Senji Shoji, Kenjiro Yasunari, Yasunobu Kosa