Patents by Inventor Senthil Thangaraj
Senthil Thangaraj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220214834Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: March 21, 2022Publication date: July 7, 2022Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 11294594Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: GrantFiled: November 1, 2017Date of Patent: April 5, 2022Assignee: Kioxia CorporationInventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 10909030Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.Type: GrantFiled: September 11, 2018Date of Patent: February 2, 2021Assignee: Toshiba Memory CorporationInventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
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Publication number: 20200081830Abstract: In an SSD including a host interface, controller, non-volatile memory coupled to the controller, and volatile memory, data is stored in non-volatile memory in clusters having a cluster start address and a cluster end address. A mapping table is maintained in volatile memory, which indicates by a trim signature deallocated clusters in non-volatile memory. The trim table is populated with deallocated ranges and an associated offset within the non-volatile memory. The controller receives from the host interface a sequence of commands including a deallocate command including at least one address range including a start address and an end address, or a start address and a length of the address range. The controller processes the deallocate command by selecting one or both of a write-to-non-volatile-memory action and a record-to-volatile-memory action. In cases of power failure, the mapping table is restored for deallocated ranges at specific offsets recorded in the trim table.Type: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Inventors: Girish Desai, Saswati Das, Senthil Thangaraj, Barada Mishra, Julien Magretts, Philip Rose
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Publication number: 20190042150Abstract: In one embodiment, a solid state drive (SSD) comprises a plurality of non-volatile memory dies communicatively arranged in one or more communication channels, each of the plurality of non-volatile memory dies comprising a plurality of physical blocks, one or more channel controllers communicatively coupled to the one or more communication channels, respectively, and a memory controller communicatively coupled to the plurality of non-volatile memory dies via the one or more channel controllers, wherein the memory controller is configured to assign (i) the plurality of physical blocks of a first die of the plurality of non-volatile memory dies to only a first region and (ii) the plurality of physical blocks of a second die of the plurality of non-volatile memory dies to only a second region, perform only read operations on the first region in a first operation mode, and perform write operations or maintenance operations on the second region in a second operation mode concurrently with read operations on the firType: ApplicationFiled: November 1, 2017Publication date: February 7, 2019Inventors: Steven Wells, Mark Carlson, Amit Jain, Narasimhulu Dharani Kotte, Senthil Thangaraj, Barada Mishra, Girish Desai
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Patent number: 8468524Abstract: Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while processing the hardware timer interrupt. The timer value may be based on a kernel timing parameter maintained by the operating system of the first virtual machine. A second virtual machine may read the shared timer value from the shared memory location in order to time inter-virtual machine processes such as I/O processing and I/O requests.Type: GrantFiled: October 13, 2010Date of Patent: June 18, 2013Assignee: LSI CorporationInventors: Vinu Velayudhan, Varadaraj Talamacki, Senthil Thangaraj, Sumant Kumar Patro
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Patent number: 8417862Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.Type: GrantFiled: October 13, 2010Date of Patent: April 9, 2013Assignee: LSI CorporationInventors: Varadaraj Talamacki, Vinu Velayudhan, Senthil Thangaraj, Sumant Kumar Patro
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Publication number: 20120124355Abstract: Disclosed is a method of booting a virtual machine. A file, accessible by a privileged domain that includes an index file image and a plurality of other file images is stored. The index file image is of a predetermined, fixed size and includes a file name and a file size for each of the other images in the file. The privileged domain provides the file to one or more non-privileged virtual machines as a single disk image of the fixed size mounted on the non-privileged virtual machine. The other file images are extracted by the virtual machines based on the file names and file sizes stored in the index file image.Type: ApplicationFiled: November 11, 2010Publication date: May 17, 2012Inventors: Sumant Kumar Patro, Varadaraj Talamacki, Vinu Velayudhan, Senthil Thangaraj
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Publication number: 20120096205Abstract: Disclosed is a virtual machine system where hardware timer interrupts are processed by a first virtual machine. The first virtual machine writes a timer value to a shared memory location while processing the hardware timer interrupt. The timer value may be based on a kernel timing parameter maintained by the operating system of the first virtual machine. A second virtual machine may read the shared timer value from the shared memory location in order to time inter-virtual machine processes such as I/O processing and I/O requests.Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Inventors: Vinu Velayudhan, Varadaraj Talamacki, Senthil Thangaraj, Sumant Kumar Patro
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Publication number: 20120096206Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.Type: ApplicationFiled: October 13, 2010Publication date: April 19, 2012Inventors: Varadaraj Talamacki, Vinu Velayudhan, Senthil Thangaraj, Sumant Kumar Patro
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Publication number: 20070088928Abstract: Methods and systems for improved lock processing in a storage controller. Storage controllers that provide storage management features such as RAID storage controllers may concurrently process I/O requests received from attached host systems and I/O requests generated internally by the management processing in the controller. Such concurrent processing is coordinated by lock processing that allows affected storage areas to be locked during processing of an I/O operation. Features and aspects hereof allow such lock processing to lock regions flexibly defined by the controller. The flexible definition of the regions to be locked allows variance in the granularity of the locks required. Smaller granularity permits more concurrent I/O requests to be processed.Type: ApplicationFiled: October 19, 2005Publication date: April 19, 2007Inventors: Senthil Thangaraj, Paresh Chatterjee, Basavaraj Hallyal
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Publication number: 20070074082Abstract: System and methods are disclosed for gathering debug information of a storage system of a computer system without requiring additional external hardware directly connected to the controller of the storage system.Type: ApplicationFiled: September 23, 2005Publication date: March 29, 2007Inventors: Senthil Thangaraj, Paresh Chatterjee
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Publication number: 20070067501Abstract: A plurality of modes is provided for communicating between a host system and a peripheral storage system controller. A first communication mode may be selected from the plurality of communication modes based on a bit length required to communicate a physical address. During runtime, a switch from the first communication mode to a second communication mode may be performed in order to improve the efficiency of processing address requests at the storage system controller.Type: ApplicationFiled: September 22, 2005Publication date: March 22, 2007Inventors: Parag Maharana, Senthil Thangaraj, Gerald Smith
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Publication number: 20070028041Abstract: Systems, apparatuses, and methods are described for performing diagnostic testing in a RAID environment in response to a failed memory access request to determine if a hard drive within the RAID failed.Type: ApplicationFiled: July 26, 2005Publication date: February 1, 2007Inventors: Basavaraj Hallyal, Senthil Thangaraj, Ragendra Mishra
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Patent number: 7117310Abstract: Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.Type: GrantFiled: February 18, 2004Date of Patent: October 3, 2006Assignee: LSI Logic CorporationInventors: Paresh Chatterjee, Chayan Biswas, Ragendra Mishra, Senthil Thangaraj
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Publication number: 20060200595Abstract: The invention relates to a method for computer signal processing data and command transfer over an interface and more particularly to a communication between peripheral firmware and a host processor or Basic Input/Output System (BIOS) on a Peripheral Component Interconnect (PCI) bus. In one embodiment, a device and method for reducing the load on the PCI Bus is described. In yet another embodiment, a device and method is described for constructing a variable length command block comprising message frames and aligning all message frames for a particular command block that are contiguous in memory.Type: ApplicationFiled: March 2, 2005Publication date: September 7, 2006Inventors: Parag Maharana, Basavaraj Hallyal, Senthil Thangaraj, Gurpreet Anand
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Publication number: 20050182906Abstract: Systems and methods for maintaining cache coherency between a first controller and a redundant peer controller while reducing communication overhead processing involved in the coherency message exchange. Header or meta-data information is accumulated in a buffer in a first controller along with updated cache data (if any) and forwarded to the peer controller. The accumulating information may be double buffered so that a buffer is filling as a previously filled buffer is transmitting to the peer controller. The peer controller processes the received information to update its mirror cache to maintain coherency with the first controller's cache memory with respect to dirty data. The method and systems avoid the need to update cache coherency in response to every flush operation performed within the first controller to thereby improve overall system performance.Type: ApplicationFiled: February 18, 2004Publication date: August 18, 2005Inventors: Paresh Chatterjee, Chayan Biswas, Ragendra Mishra, Senthil Thangaraj
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Publication number: 20050086429Abstract: A mechanism is provided for migration between stripe storage and redundant parity striped storage. When a disk is added to a disk array, the mechanism migrates from RAID 0 to RAID 5. For each row, the mechanism calculates parity for the row and, if the parity position is not the new drive, the mechanism writes the data from the parity position to the new drive and writes the parity to the parity stripe position. If a drive fails, the mechanism migrates back from RAID 5 to RAID 0. For each row, if the parity position is not the failed drive, reads the data from remaining drives, XORs the data stripes to get failed drive data, and writes the failed drive data to the parity position. If a read or write is received for the failed drive, the mechanism simply redirects the read or write to the parity position.Type: ApplicationFiled: October 15, 2003Publication date: April 21, 2005Inventors: Paresh Chatterjee, Basavaraj Hallyal, Senthil Thangaraj, Narasimhulu Kotte, Ramya Subramanian