Patents by Inventor Senthil Velan K

Senthil Velan K has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CIRCUIT FOR GENERATING MULTI-PHASE NON-OVERLAPPING CLOCK SIGNALS
    Publication number: 20130187696
    Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.
    Type: Application
    Filed: January 23, 2012
    Publication date: July 25, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Siddhartha Gopal Krishna, Senthil Velan K
  • Circuit for generating multi-phase non-overlapping clock signals
    Patent number: 8487683
    Abstract: A circuit for generating multi-phase, non-overlapping clock signals includes a shift register that generates first and second clock signals from an input clock signal. First and second circuit modules generate corresponding first and second interim signals using the first and second clock signals and first and second feedback signals, respectively. The first and second interim signals are non-overlapping by at least a predetermined minimum time difference. The first and second interim signals are multiplexed to generate an output signal. The output signal is delayed by a first predetermined time to generate a first delay signal. The first delay signal is delayed by a second predetermined time to generate a second delay signal. The second delay signal is de-multiplexed to generate the first and the second feedback signals, and the first delay signal is de-multiplexed to generate the set of multi-phase, non-overlapping clock signals.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: July 16, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Siddhartha Gopal Krishna, Senthil Velan K