Abstract: Systems and methods are provided for generating a soft information metric corresponding to a bit stored in a memory. The systems and methods include comparing a symbol value associated with the stored bit to a plurality of decision thresholds to obtain a plurality of binary values. One of the plurality of binary values is selected to obtain a reference value. Further, a frequency metric is computed, which corresponds to the number of times each of the plurality of binary values equals a predefined value. The soft information metric is then determined based on the frequency metric and the reference value.

Abstract: Systems and methods are provided for generating a soft information metric corresponding to a bit stored in a memory. The systems and methods include comparing a symbol value associated with the stored bit to a plurality of decision thresholds to obtain a plurality of binary values. One of the plurality of binary values is selected to obtain a reference value. Further, a frequency metric is computed, which corresponds to the number of times each of the plurality of binary values equals a predefined value. The soft information metric is then determined based on the frequency metric and the reference value.

Abstract: The present disclosure includes systems and techniques relating to the use of evolutionary algorithms for tuning the performance of read channels. Instructions encoded on a medium are performed by processor cause a storage device to perform operations including obtaining values corresponding to operating parameters of a read channel of the storage device, generating one or more output parameters corresponding to use of the values with the read channel, selecting a proper subset of the values based on the one or more output parameters and a cost function, creating a new generation of the values corresponding to the operating parameters based on the proper subset and repeating the generating and the selecting using the new generation of the values until a target is achieved, and outputting two or more of the values of the proper subset of a last generation, when the target is achieved to configure the read channel.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.

Abstract: A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: Systems and methods for constructing concatenated codes for data storage channels, such as holographic storage channels, are provided. The concatenated codes include an outer BCH code and an inner iteratively decodable code, such as an LDPC code or turbo code. The correction power and coding rate of one or both of the codes may be programmable based on the channel characteristics and the desired SNR coding gain. The correction power and/or coding rate of the inner and/or outer code may also be dynamically adjusted in real-time to compensate for time-varying error conditions on the channel.

Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.

Abstract: Embodiments of the present invention provide a read channel including a front end to receive an optical image, convert the optical image into multi-bit soft information, and to serially transmit the multi-bit soft information to other components of the read channel. Other embodiments may be described and claimed.

Abstract: Systems, methods, and apparatus are provided for increasing decoding throughput in an LDPC decoder, such as in a wireless communications receiver or in a data retrieval unit. A checker-board parity check matrix and edge-based LDPC decoder structure are provided in which both vertical and horizontal processors are used simultaneously. Horizontal processors may be grouped into type-A and type-B horizontal processors, and similarly, vertical processors may be grouped into type-A and type-B vertical processors. Type-A processors may be used in different clock cycles than type-B processors to update memory locations in a decoding matrix without causing memory access conflicts.

Abstract: Some of the embodiments of the present disclosure provide a system, device and a method performing N read cycles on a plurality of memory cells of a memory sector, wherein N is an integer greater than one; constructing (N+1) bin histograms based at least in part on performing the N read cycles; identifying a shortest bin histogram of the (N+1) bin histograms; and based on a height of the shortest histogram, assigning a log-likelihood ratio (LLR) to the shortest bin histogram. Other embodiments are also described and claimed.

Abstract: A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.

Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

Abstract: Systems and methods for constructing low-density parity check codes for holographic storage are provided. The methods include selecting parameters of a low-density parity check code, determining the number of bit processing elements and the amount of memory in an accompanying decoder, and constructing a mother matrix representation of a quasi-cyclic parity check matrix. The low-density parity check codes are optimized for performance, memory considerations, and throughput.

Abstract: A system and method is provided for performing concatenated error correction. In one implementation, an apparatus for encoding data includes an outer encoder to generate a code word corresponding to received input data and a parity circuit to compute parities of logical cells of data, the logical cells of data being obtained from the code word and having a first logical cell. The apparatus also includes an inner encoder to generate an error correction bit for the first logical cell based on a first parity corresponding to the first logical cell, and to insert the error correction bit in the first logical cell.

Abstract: Embodiments of the present invention provide a read channel including a front end to receive an optical image, convert the optical image into multi-bit soft information, and to serially transmit the multi-bit soft information to other components of the read channel. Other embodiments may be described and claimed.

Abstract: A non-linear detector for detecting signals with signal-dependent noise is disclosed. The detector may choose a data sequence that maximizes the conditional probability of detecting the channel data. Since the channel may be time-varying and the precise channel characteristics may be unknown, the detector may adapt one or more branch metric parameters before sending the parameters to a loading block. In the loading block, the branch metric parameters may be normalized and part of the branch metric may be pre-computed to reduce the complexity of the detector. The loading block may then provide the branch metric parameters and any pre-computation to the detector. The detector may then calculate the branch metric associated with the input signal and output the channel data.