Abstract: A wafer cleaning method is provided. The wafer cleaning method includes providing a wafer on a stage that is inside of a chamber. The wafer is fixed to the stage by moving a grip pin connected to an edge of the stage. First ultrapure water is supplied onto the wafer while the wafer is rotating at a first rotation speed. The grip pin is released from the wafer by moving the grip pin. A development process is performed by supplying liquid chemical onto the wafer while the wafer is rotating at a second rotation speed that is less than the first rotation speed.

Abstract: A display device includes a display layer comprising pixels, each of the pixels having at least one thin-film transistor, a connection line electrically connected to the at least one thin-film transistor, the connection line being exposed on a lower surface of the display layer through a first contact hole formed in the display layer, a barrier layer disposed on the lower surface of the display layer and including a second contact hole connected to the first contact hole, a lead line disposed on a lower surface of the barrier layer and electrically connected to the connection line through the second contact hole, a pad part disposed on the lower surface of the barrier layer and electrically connected to the lead line, and a lower film overlapping the lower surface of the barrier layer and the lead line.

Abstract: An antibody binds to CD154. The antibody includes HCDR, which includes amino acid sequences of SEQ ID NOs: 1 to 3, and LCDR which includes amino acid sequences of SEQ ID NOs: 4 to 6. A composition including an antibody-drug conjugate in which a drug is conjugated to the antibody may prevent or treat a T cell-mediated autoimmune disease and/or organ transplant rejection.

Abstract: A reflective mask includes a first reflection layer disposed on a mask substrate, a first capping layer disposed on the first reflection layer, a second reflection pattern disposed on a portion of the first capping layer, and a phase shifter disposed between the second reflection pattern and the first capping layer to cause a phase difference between a first light reflecting from the first reflection layer and a second light reflecting from the second reflection pattern. Related methods are also provided.

Abstract: A reflective mask includes a first reflection layer disposed on a mask substrate, a first capping layer disposed on the first reflection layer, a second reflection pattern disposed on a portion of the first capping layer, and a phase shifter disposed between the second reflection pattern and the first capping layer to cause a phase difference between a first light reflecting from the first reflection layer and a second light reflecting from the second reflection pattern. Related methods are also provided.

Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

Abstract: A method for forming a pattern in a semiconductor device includes performing a double exposure process for a multifunctional hard mask layer over a semiconductor substrate using a line/space mask to form a multifunctional hard mask layer pattern having a first contact hole region. The multifunctional hard mask layer pattern is subjected to a resist flow process to form a multifunctional hard mask layer pattern having a second contact hole region with rounded edges, where the size of the second contact hole region is smaller than that of the first contact hole region.

Abstract: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process margin of semiconductor devices and the reliability of semiconductor devices.

Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.

Abstract: An exposure mask for forming a G-type active region with a double patterning technology includes a bar shaped first light-blocking pattern to define an I-type active region, and an island shaped second light-blocking pattern to define a bit line contact region. The first light-blocking pattern and the second light-blocking pattern are arranged alternately.

Abstract: A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern.

Abstract: A method for forming a pattern in a semiconductor device includes performing a double exposure process for a multifunctional hard mask layer over a semiconductor substrate using a line/space mask to form a multifunctional hard mask layer pattern having a first contact hole region. The multifunctional hard mask layer pattern is subjected to a resist flow process to form a multifunctional hard mask layer pattern having a second contact hole region with rounded edges, where the size of the second contact hole region is smaller than that of the first contact hole region.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: A method for forming a semiconductor device includes forming a bit line contact region with a line pattern and then performing a process to form a bit line so that a multi-layered bit line contact is expended, thereby preventing a short between bit line contact plugs and improving the process margin of semiconductor devices and the reliability of semiconductor devices.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer and the size of the capacitor are factors for increasing parasitic capacitance and leakage currents. Also, the two capacitors are arranged diagonally, thereby widening the width of each capacitor formed. Furthermore, in case of forming the double capacitors according to the preferred embodiment of the present invention, an additional reticle is not required to form the contact holes for each capacitor due to their inverted disposition relationship.

Abstract: Disclosed are a memory device and a method for fabricating the same. The memory device includes: a substrate provided with a trench; a bit line contact junction formed beneath the trench; a plurality of storage node contact junctions formed outside the trench; and a plurality of gate structures each being formed on the substrate disposed between the bit line contact junction and one of the storage node contact junctions. Each sidewall of the trench becomes a part of the individual channels and thus, channel lengths of the transistors in the cell region become elongated. Accordingly, the storage node contact junctions have a decreased level of leakage currents, thereby increasing data retention time.

Abstract: The present invention relates to a semiconductor memory device and a method for fabricating the same. Particularly, the semiconductor memory device includes at least more than two capacitors to decrease the thickness of an insulation layer and increase the size of each capacitor, wherein the thickness of the insulation layer and the size of the capacitor are factors for increasing parasitic capacitance and leakage currents. Also, the two capacitors are arranged diagonally, thereby widening the width of each capacitor formed. Furthermore, in case of forming the double capacitors according to the preferred embodiment of the present invention, an additional reticle is not required to form the contact holes for each capacitor due to their inverted disposition relationship.

Abstract: The present invention relates to a method for fabricating a recessed gate structure. The method includes the steps of: selectively etching a substrate to form a plurality of openings; forming a gate oxide layer on the openings and the substrate; forming a first conductive silicon layer on the gate oxide layer to form a plurality of valleys at a height equal to or greater than a thickness remaining after an intended pattern is formed; planarizing the first conductive silicon layer until the thickness remaining after the intended pattern formation is obtained, so that the valleys are removed; forming a second conductive layer on a planarized first conductive silicon layer; and selectively etching the second conductive layer, the first conductive silicon layer and the gate oxide layer to form a plurality of the recessed gate structures.