Abstract: A multi-block erase circuit in nonvolatile semiconductor memory device comprises a plurality of memory blocks composed of a plurality of memory cells formed on a semiconductor substrate, each memory cell composed of at least one memory transistor with a floating gate and a control gate, and a plurality of block selectors connected to the memory blocks to select the control gates of the memory transistors within a selected memory block and to erase the memory transistors during an erase operation, wherein each block selector has storing means for storing block selection flags to select the control gates of the memory transistors within at least one selected memory block during the erase operation and for storing reset flags to float the control gates of the memory transistors within the remaining unselected memory blocks, thereby erasing simultaneously only the memory transistors within the selected memory blocks during the erase operation.

Abstract: A nonvolatile semiconductor memory having a common source line driving circuit which simply ensures a sufficient threshold voltage margin for erased memory cells during an erase verifying operation. The nonvolatile semiconductor memory includes a resistance which cause, during an erase verifying operation of the memory after erasure of the memory cells, an erase verifying potential to develop on the common source line, allowing verification that each memory cell has a predetermined threshold voltage. The erase verifying voltage is developed across the resistance in response to a predetermined current supplied from a current source circuit connected to the bit line, and flowing through the drain-source paths of memory cells which are series-connected between the bit line and the current source line.

Abstract: Integrated circuit memory devices having interleaved read capability include read controllers and subpage data buffers for performing interleaved read operations. These read operations are performed by downloading respective subpages of memory while simultaneously serially transmitting previously downloaded subpages of memory so that consecutive pages of memory data can be serially transmitted as a continuous string of data without the occurrence of breaks therebetween caused by stand-by holding periods. These memory devices typically contain an array of memory cells arranged as a plurality of pages (e.g., rows) of predetermined width coupled to a respective plurality of word lines and a plurality of columns of memory cells electrically coupled to a respective plurality of bit lines. First and second subpage buffers may also be provided for temporarily storing subpages of data read from addressed subpages of memory cells.