Abstract: A memory card identification device, a host device using the memory card, and a memory card are provided. The memory card identification device includes: a card socket comprising a single card slot through which at least two kinds of memory cards can be inserted and a target port disposed to be in contact with any one kind of a target memory card based on an external characteristic difference between different kinds of memory cards; and a card type detector configured to determine a type of a memory card inserted in the card socket by using a contact state signal of the target port.

Abstract: Disclosed are a method and apparatus for decolorization of reactive anthraquinone dye-containing wastewater using photocatalytic oxidation, which include inducing high-efficiency photocatalytic oxidation under a controlled salt concentration and pH of wastewater to perform effective decolorization of reactive anthraquinone dye-containing wastewater. The method for decolorization of reactive anthraquinone dye-containing wastewater using photocatalytic oxidation, includes: introducing a photocatalyst and salt into reactive anthraquinone dye-containing wastewater and adjusting pH of the wastewater to a level higher than neutral pH; and irradiating UV to the photocatalyst to carry out cleavage of the reactive anthraquinone dyes through photocatalytic oxidation, thereby accomplishing decolorization of wastewater.

Abstract: In one embodiment, the memory device includes a first memory area and a second memory area. The first memory area stores secure data. The first memory area is inaccessible by an external device. The second memory area is configured to store encrypted secure data. The second memory area is accessible by the external device, and the encrypted secure data is an encrypted version of the secure data in the first memory area.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: Disclosed are a method and apparatus for decolorization of reactive anthraquinone dye-containing wastewater using photocatalytic oxidation, which include inducing high-efficiency photocatalytic oxidation under a controlled salt concentration and pH of wastewater to perform effective decolorization of reactive anthraquinone dye-containing wastewater. The method for decolorization of reactive anthraquinone dye-containing wastewater using photocatalytic oxidation, includes: introducing a photocatalyst and salt into reactive anthraquinone dye-containing wastewater and adjusting pH of the wastewater to a level higher than neutral pH; and irradiating UV to the photocatalyst to carry out cleavage of the reactive anthraquinone dyes through photocatalytic oxidation, thereby accomplishing decolorization of wastewater.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and user data for the computer system; and an interface unit communicating with the system controller through the system bus in the first interface mode and communicating with the NAND flash memory in a second interface mode, the interface unit being synchronized with a clock signal generated therein in response to predetermined command and operating information. The NAND flash memory may be used for the system bootstrap, and data transmission to the system controller during reading or programming operations is performed successively to reduce the latency time on the read operation and the data loading time on the programming operation.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and user data for the computer system; and an interface unit communicating with the system controller through the system bus in the first interface mode and communicating with the NAND flash memory in a second interface mode, the interface unit being synchronized with a clock signal generated therein in response to predetermined command and operating information. The NAND flash memory may be used for the system bootstrap, and data transmission to the system controller during reading or programming operations is performed successively to reduce the latency time on the read operation and the data loading time on the programming operation.

Abstract: A non-volatile semiconductor memory device and/or a data processing system include a non-volatile memory array having a plurality of memory blocks and a write-protection control circuit that controls access to blocks of memory based on a start block address and an end block address. The write-protection control circuit may store start and end block addresses of an unlock region of the non-volatile memory array, and selectively activate a write enable signal according to the relationship between a write address and the start and end block addresses.

Abstract: A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Abstract: Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

Abstract: Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

Abstract: A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Abstract: A non-volatile semiconductor memory device and/or a data processing system include a non-volatile memory array having a plurality of memory blocks and a write-protection control circuit that controls access to blocks of memory based on a start block address and an end block address. The write-protection control circuit may store start and end block addresses of an unlock region of the non-volatile memory array, and selectively activate a write enable signal according to the relationship between a write address and the start and end block addresses.

Abstract: A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and user data for the computer system; and an interface unit communicating with the system controller through the system bus in the first interface mode and communicating with the NAND flash memory in a second interface mode, the interface unit being synchronized with a clock signal generated therein in response to predetermined command and operating information. The NAND flash memory may be used for the system bootstrap, and data transmission to the system controller during reading or programming operations is performed successively to reduce the latency time on the read operation and the data loading time on the programming operation.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: A semiconductor memory device includes page buffers having load transistors, each of which supplies load current to bitlines. The device also has a load control circuit, which is commonly connected to gates of the load transistor, having two discharge paths. The load control circuit discharges the gate voltage via the first discharge path when a gate voltage applied to the gates in read operation is higher than a target voltage, and discharges the gate voltage via the second discharge path when the gate voltage arrives at the target voltage. Therefore, it is possible to quickly set the gate voltage to the target voltage.