Patents by Inventor Seok-Hong Kwon
Seok-Hong Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240092592Abstract: The present invention relates to a particle transfer system and a particle transfer method which allow preciously-weighed particles to smoothly pass through a vertically-provided vertical pipe of a transfer line when powder-type particles are transferred along the transfer line, and which prevent the particles from remaining or stagnating in the vertical pipe.Type: ApplicationFiled: November 30, 2021Publication date: March 21, 2024Inventors: Sang Hong LEE, In Seok JUNG, Eui Jip CHOI, Tai Yeon KWON, Kyung Seob LIM
-
Patent number: 10141293Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: GrantFiled: December 29, 2017Date of Patent: November 27, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
-
Publication number: 20180122790Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Seok-hong KWON, Sang-nam JEONG, Sun-won KANG, Hee-jin LEE
-
Patent number: 9899361Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.Type: GrantFiled: September 1, 2016Date of Patent: February 20, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyoungjoon Kim, Kwangil Park, Seok-Hong Kwon, Chulsung Park, Eunsung Seo, Heejin Lee, Kijong Park
-
Patent number: 9859263Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: GrantFiled: August 17, 2016Date of Patent: January 2, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Seok-hong Kwon, Sang-nam Jeong, Sun-won Kang, Hee-jin Lee
-
Publication number: 20170141092Abstract: A semiconductor package includes a logic chip mounted on a substrate, a first memory chip disposed on the logic chip, which includes a first active surface, and a second memory chip disposed on the first memory chip. The second memory chip is disposed on the first memory chip in such a way that the first memory chip and second memory chip are offset from each other. The second memory chip has a second active surface. The first active surface and the second active surface face each other and are electrically connected to each other through a first solder bump.Type: ApplicationFiled: September 1, 2016Publication date: May 18, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Hyoungjoon Kim, Kwangil PARK, Seok-Hong KWON, Chulsung PARK, Eunsung SEO, Heejin LEE, Kijong PARK
-
Publication number: 20170125393Abstract: A semiconductor package includes a package base substrate including bonding pads and a connection pads respectively on an upper surface and a lower surface of the package base substrate, four semiconductor chips attached onto the package base substrate, including a 1A semiconductor chip, a 1B semiconductor chip, a 2A semiconductor chip, and a 2B semiconductor chip, and each including a plurality of chip pads that are adjacent to a first edge of an upper surface of each of the 1A semiconductor chip, the 1B semiconductor chip, the 2A semiconductor chip, and the 2B semiconductor chip, and a bonding wire electrically connecting the chip pad and the bonding pad to each other, wherein the four semiconductor chips are disposed on the package base substrate such that first edges of the four semiconductor chips respectively face edges of the package base substrate that are different from each other.Type: ApplicationFiled: August 17, 2016Publication date: May 4, 2017Inventors: Seok-hong KWON, Sang-nam JEONG, Sun-won KANG, Hee-jin LEE
-
Patent number: 9466593Abstract: A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.Type: GrantFiled: December 29, 2015Date of Patent: October 11, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dae-Ho Lee, Hyo-Soon Kang, Seok-Hong Kwon, Tae-Young Yoon, Hee-Jin Lee
-
Publication number: 20160190109Abstract: A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.Type: ApplicationFiled: December 29, 2015Publication date: June 30, 2016Inventors: Dae-Ho Lee, Hyo-Soon Kang, Seok-Hong Kwon, Tae-Young Yoon, Hee-Jin Lee