Patents by Inventor Seokhyeon YOON
Seokhyeon YOON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973082Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.Type: GrantFiled: August 24, 2021Date of Patent: April 30, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Seokhyeon Yoon, Junyoung Park, Woocheol Shin, Seunghun Lee
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Publication number: 20240113110Abstract: A semiconductor device includes first and second active patterns on first and second PMOS regions, two first source/drain patterns spaced apart along a first direction on the first active pattern and a first channel pattern including first semiconductor patterns between the two first source/drain patterns, and two second source/drain patterns spaced apart along the first direction on the second active pattern and a second channel pattern including second semiconductor patterns between the two second source/drain patterns. A width in a second direction of the each of the first semiconductor patterns is greater than a width of each of the second semiconductor patterns. Each of the first and second source/drain patterns includes semiconductor layers having different germanium concentrations. A number of the semiconductor layers of each of the two second source/drain patterns is greater than a number of the semiconductor layers of each of the two first source/drain patterns.Type: ApplicationFiled: May 18, 2023Publication date: April 4, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyung Hee CHO, Seokhyeon YOON, Hyeongrae KIM, Jeewoong SHIN
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Publication number: 20240049438Abstract: A semiconductor device includes a substrate, a SRAM cell including a pass-gate transistor, a pull-down transistor, and a pull-up transistor on substrate. The SRAM cell includes an active fin extending in a first direction, the pass-gate transistor and the pull-down transistor are disposed adjacent to each other on the active fin in the first direction, the pass-gate transistor includes first channel layers, a first gate electrode, first source/drain regions, and first inner spacers, the pull-down transistor includes second channel layers, a second gate electrode, second source/drain regions, and second inner spacers, and one of the first inner spacers and one of the second inner spacers are disposed on the same height level and have different thicknesses in the first direction.Type: ApplicationFiled: March 1, 2023Publication date: February 8, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seunghun Lee, Seokhyeon Yoon, Kyowook Lee, Hyejin Lee
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Patent number: 11881509Abstract: The semiconductor device may include an active pattern provided on a substrate and a source/drain pattern on the active pattern. The source/drain pattern may include a bottom surface in contact with a top surface of the active pattern. The semiconductor device may further include a channel pattern connected to the source/drain pattern, a gate electrode extended to cross the channel pattern, and a fence insulating layer extended from a side surface of the active pattern to a lower side surface of the source/drain pattern. A pair of middle insulating patterns may be at both sides of the bottom surface of the source/drain pattern and between the active pattern and the source/drain pattern in contact with an inner side surface of the fence insulating layer.Type: GrantFiled: August 9, 2021Date of Patent: January 23, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Junbeom Park, Sangmo Koo, Minyi Kim, Seokhyeon Yoon
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Publication number: 20240006485Abstract: A semiconductor device include first and second active patterns, first and second gate structures, and first and second source/drain layers. The first and second active patterns extend on the first and second regions in a first direction. The first and second gate structures are formed on the first and second active patterns, and extend in a second direction. The first and second source/drain layers are formed on the first and second active patterns adjacent to the first and second gate structures. The first active pattern includes a first well having first and second impurity regions. The second active pattern includes a second well having third and fourth impurity regions. A width in the second direction of the first impurity region is greater than that of the second impurity region. A width in the second direction of the third impurity region is smaller than that of the fourth impurity region.Type: ApplicationFiled: May 11, 2023Publication date: January 4, 2024Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seokhyeon Yoon, Taehyeon Kim, Seunghun Lee, Hyeongrae Kim
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Publication number: 20220208790Abstract: An integrated circuit device includes: a semiconductor on insulator (SOI) substrate layer including a base substrate layer, an insulating substrate layer, and a cover substrate layer; a semiconductor substrate layer; a plurality of first fin-type active areas and a plurality of second fin-type active areas each defined by a plurality of trenches, and extending in a first horizontal direction, in above the SOI substrate layer and the semiconductor substrate layer, respectively; a plurality of nanosheet stacked structures comprising nanosheets extending in parallel with each other and spaced apart from upper surfaces of the plurality of first fin-type active areas and the plurality of second fin-type active areas; a plurality of first source/drain regions extending into the SOI substrate layer; and a plurality of second source/drain regions extending into the semiconductor substrate layer. Lower surfaces of the first and second source/drain regions may not be coplanar with each other.Type: ApplicationFiled: August 24, 2021Publication date: June 30, 2022Inventors: Seokhyeon Yoon, Junyoung Park, Woocheol Shin, Seunghun Lee
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Publication number: 20220199775Abstract: The semiconductor device may include an active pattern provided on a substrate and a source/drain pattern on the active pattern. The source/drain pattern may include a bottom surface in contact with a top surface of the active pattern. The semiconductor device may further include a channel pattern connected to the source/drain pattern, a gate electrode extended to cross the channel pattern, and a fence insulating layer extended from a side surface of the active pattern to a lower side surface of the source/drain pattern. A pair of middle insulating patterns may be at both sides of the bottom surface of the source/drain pattern and between the active pattern and the source/drain pattern in contact with an inner side surface of the fence insulating layer.Type: ApplicationFiled: August 9, 2021Publication date: June 23, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Junbeom PARK, Sangmo KOO, Minyi KIM, Seokhyeon YOON