Patents by Inventor Seok Il Youn

Seok Il Youn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8607118
    Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho
  • Patent number: 8347194
    Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho
  • Publication number: 20090307566
    Abstract: An iterative decoding method is disclosed and includes sequentially executing a number of iterative decoding cycles in relation to a parity check equation until the parity check equation is resolved, or a maximum number N of iterative decoding cycles is reached, during execution of the number of iterative decoding cycles, storing in a data buffer minimum estimated values for a set of variable nodes corresponding to a minimum number of bit errors, and outputting the minimum estimated values stored in the data buffer as a final decoding result when the number of iterative decoding cycles reaches N.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 10, 2009
    Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Seoul National University
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho
  • Publication number: 20090282319
    Abstract: A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
    Type: Application
    Filed: April 23, 2009
    Publication date: November 12, 2009
    Applicants: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Seoul National University
    Inventors: Jong Seon No, Beom Kyu Shin, Seok Il Youn, Jae Dong Yang, Jun Jin Kong, Jae Hong Kim, Yong June Kim, Kyoung Lae Cho